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Temporal logic based hardware description and its verification with Prolog

https://doi.org/10.1007/bf03037426
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-94-009-7893-5_6openalex-snapshot
Verification of Sequential Programs: Temporal Axiomatization
inferredcites →https://doi.org/10.1016/s0019-9958(83)80051-5openalex-snapshot
Temporal logic can be more expressive
inferredcites →https://doi.org/10.1109/dac.1979.1600139openalex-snapshot
The Application of Program Verification to Hardware Verification
inferredcites →https://doi.org/10.1109/dac.1982.1585588openalex-snapshot
A formal method for computer design verification
inferredcites →https://doi.org/10.1109/sfcs.1981.44openalex-snapshot
Temporal logic can be more expressive
inferredcites →https://doi.org/10.1109/tc.1982.1675978openalex-snapshot
Hardware Specification with Temporal Logic: An Example
inferredcites →https://doi.org/10.1145/567067.567080openalex-snapshot
Automatic verification of finite state concurrent system using temporal logic specifications
inferredcites →https://doi.org/10.5555/800263.809294openalex-snapshot
A formal method for computer design verification

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-16479-0_14openalex-snapshot
Implementation of temporal logic programming language Tokio
inferred← citeshttps://doi.org/10.1007/3-540-19426-6_19openalex-snapshot
Test generation for large-scale combinational circuits by using Prolog
inferred← citeshttps://doi.org/10.1007/978-94-009-5044-3_13openalex-snapshot
Other Application Areas of Logic Programming
inferred← citeshttps://doi.org/10.1007/bf03037053openalex-snapshot
Description and Reasoning of VLSI circuit in temporal logic
inferred← citeshttps://doi.org/10.1016/0045-7906(90)90018-bopenalex-snapshot
Design verification of digital systems based on logic programming
inferred← citeshttps://doi.org/10.1016/0165-6074(89)90040-9openalex-snapshot
Formal hardware specification and verification using prolog
inferred← citeshttps://doi.org/10.1016/0165-6074(89)90189-0openalex-snapshot
PROLOG as a formalism for VLSI design specification
inferred← citeshttps://doi.org/10.1016/0743-1066(84)90024-4openalex-snapshot
A KWIC (key word in context) bibliography on prolog and logic programming
inferred← citeshttps://doi.org/10.1109/2.65openalex-snapshot
Formal verification of hardware correctness: introduction and survey of current research
inferred← citeshttps://doi.org/10.1109/asap.1991.238910openalex-snapshot
Automatic formal verification of systolic array designs
inferred← citeshttps://doi.org/10.1109/cmpeur.1991.257403openalex-snapshot
A functional-based approach to formal VLSI design verification
inferred← citeshttps://doi.org/10.1109/dac.1986.1586091openalex-snapshot
Reasoning about Digital Systems Using Temporal Logic
inferred← citeshttps://doi.org/10.1109/hicss.1992.183270openalex-snapshot
An automated design specification and verification tool for systolic architectures
inferred← citeshttps://doi.org/10.1109/mc.1985.1662795openalex-snapshot
A Temporal Logic for Multilevel Reasoning about Hardware
inferred← citeshttps://doi.org/10.1109/mc.1985.1662796openalex-snapshot
Hardware Verification
inferred← citeshttps://doi.org/10.1109/tai.1991.167030openalex-snapshot
Verification tool for systolic array design
inferred← citeshttps://doi.org/10.5555/318013.318047openalex-snapshot
Reasoning about Digital Systems Using Temporal Logic
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