On the public citation graph
A Mean Value Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques
0 signed · 34 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0166-5316(89)90046-1openalex-snapshot
Performance analysis of hierarchical cache-consistent multiprocessors
inferredcites →https://doi.org/10.1109/12.127442openalex-snapshot
Evaluating design choices for shared bus multiprocessors in a throughput-oriented environment
inferredcites →https://doi.org/10.1109/12.278481openalex-snapshot
Instruction window size trade-offs and characterization of program parallelism
inferredcites →https://doi.org/10.1109/40.210521openalex-snapshot
Research and development needs for advanced vehicle control systems
inferredcites →https://doi.org/10.1109/40.216745openalex-snapshot
Architecture of the Pentium microprocessor
inferredcites →https://doi.org/10.1109/40.216746openalex-snapshot
Performance features of the PA7100 microprocessor
inferredcites →https://doi.org/10.1109/40.216747openalex-snapshot
The Alpha AXP architecture and 21064 processor
inferredcites →https://doi.org/10.1109/spdp.1995.530681openalex-snapshot
Architecture and technology tradeoffs in the design of next-generation multiprocessor servers
inferredcites →https://doi.org/10.1145/1007771.55615openalex-snapshot
A mean-value performance analysis of a new multiprocessor architecture
inferredcites →https://doi.org/10.1145/106972.106980openalex-snapshot
High-bandwidth data memory systems for superscalar processors
inferredcites →https://doi.org/10.1145/107971.107982openalex-snapshot
Experience with mean value analysis model for evaluating shared bus, throughput-oriented multiprocessors
inferredcites →https://doi.org/10.1145/107972.107982openalex-snapshot
Experience with mean value analysis model for evaluating shared bus, throughput-oriented multiprocessors
inferredcites →https://doi.org/10.1145/191995.192029openalex-snapshot
Complexity/performance tradeoffs with non-blocking loads
inferredcites →https://doi.org/10.1145/192007.192029openalex-snapshot
Complexity/performance tradeoffs with non-blocking loads
inferredcites →https://doi.org/10.1145/55595.55615openalex-snapshot
A mean-value performance analysis of a new multiprocessor architecture
inferredcites →https://doi.org/10.1145/633625.52435openalex-snapshot
An accurate and efficient performance analysis technique for multiprocessor snooping cache-consistency protocols
inferredcites →https://doi.org/10.1145/633625.52447openalex-snapshot
The Wisconsin multicube: a new large-scale cache-coherent multiprocessor
inferredcites →https://doi.org/10.1145/98457.98754openalex-snapshot
Analysis of critical architectural and programming parameters in a hierarchical
inferredcites →https://doi.org/10.1145/98457.98756openalex-snapshot
Performance evaluation of a commercial cache-coherent shared memory multiprocessor
inferredcites →https://doi.org/10.1145/98460.98756openalex-snapshot
Performance evaluation of a commercial cache-coherent shared memory multiprocessor
inferredcites →https://doi.org/10.5555/211554.211583openalex-snapshot
Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor
inferredcites →https://doi.org/10.5555/224659.224725openalex-snapshot
An analytical model of high performance superscalar-based multiprocessors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/bfb0094909openalex-snapshot
Instruction-level microprocessor modeling of scientific applications
inferred← citeshttps://doi.org/10.1016/j.peva.2006.02.001openalex-snapshot
Determining output uncertainty of computer system models
inferred← citeshttps://doi.org/10.1016/s0166-5316(00)00051-1openalex-snapshot
Adaptive multivariate regression for advanced memory system evaluation: application and experience
inferred← citeshttps://doi.org/10.1109/iccd.2005.40openalex-snapshot
Correlation between detailed and simplified simulations in studying multiprocessor architecture
inferred← citeshttps://doi.org/10.1109/isca.1998.694797openalex-snapshot
Analytic evaluation of shared-memory systems with ILP processors
inferred← citeshttps://doi.org/10.1109/mc.2003.1178049openalex-snapshot
Queuing simulation model for multiprocessor systems
inferred← citeshttps://doi.org/10.1109/sc.2004.40openalex-snapshot
Predicting and Evaluating Distributed Communication Performance
inferred← citeshttps://doi.org/10.1109/tc.2007.38openalex-snapshot
$\log_{\rm n}{\rm P}$ and $\log_{3}{\rm P}$: Accurate Analytical Models of Point-to-Point Communication in Distributed Systems
inferred← citeshttps://doi.org/10.1109/tpds.2003.1178880openalex-snapshot
Analytic evaluation of shared-memory architectures
inferred← citeshttps://doi.org/10.1145/279358.279408openalex-snapshot
Analytic evaluation of shared-memory systems with ILP processors
inferred← citeshttps://doi.org/10.31390/gradschool_disstheses.7247openalex-snapshot
Empirical and Statistical Application Modeling Using on -Chip Performance Monitors.
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.