On the public citation graph
High-bandwidth data memory systems for superscalar processors
0 signed · 215 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.192212openalex-snapshot
High-bandwidth interleaved memories for vector processors-a simulation study
inferredcites →https://doi.org/10.1109/12.48865openalex-snapshot
Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers
inferredcites →https://doi.org/10.1109/isca.1989.714527openalex-snapshot
SIMP (single Instruction Stream/multiple Instruction Pipelining): A Novel High-speed Single-processor Architecture
inferredcites →https://doi.org/10.1109/isca.1990.134545openalex-snapshot
Boosting beyond static scheduling in a superscalar processor
inferredcites →https://doi.org/10.1109/isca.1990.134547openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1145/1067649.801719openalex-snapshot
Decoupled access/execute computer architectures
inferredcites →https://doi.org/10.1145/17356.17401openalex-snapshot
Highly concurrent scalar processing
inferredcites →https://doi.org/10.1145/18906.18916openalex-snapshot
HPS, a new microarchitecture: rationale and introduction
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
inferredcites →https://doi.org/10.1145/285930.285984openalex-snapshot
Using cache memory to reduce processor-memory traffic
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/325096.325151openalex-snapshot
Trace-driven simulations for a two-level cache design in open bus systems
inferredcites →https://doi.org/10.1145/325096.325160openalex-snapshot
Boosting beyond static scheduling in a superscalar processor
inferredcites →https://doi.org/10.1145/325096.325162openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1145/325164.325151openalex-snapshot
Trace-driven simulations for a two-level cache design in open bus systems
inferredcites →https://doi.org/10.1145/381730.381737openalex-snapshot
Bibliography and reading on CPU cache memories and related topics
inferredcites →https://doi.org/10.1145/68182.68207openalex-snapshot
Available instruction-level parallelism for superscalar and superpipelined machines
inferredcites →https://doi.org/10.1145/70082.68207openalex-snapshot
Available instruction-level parallelism for superscalar and superpipelined machines
inferredcites →https://doi.org/10.1145/74925.74935openalex-snapshot
SIMP (Single Instruction stream/Multiple instruction Pipelining): a novel high-speed single-processor architecture
inferredcites →https://doi.org/10.1145/800046.801647openalex-snapshot
Using cache memory to reduce processor-memory traffic
inferredcites →https://doi.org/10.1145/88237.88243openalex-snapshot
Cache performance of the integer SPEC benchmarks on a RISC
inferredcites →https://doi.org/10.1147/rd.341.0037openalex-snapshot
Machine organization of the IBM RISC System/6000 processor
inferredcites →https://doi.org/10.5555/62504.62535openalex-snapshot
Hardware support for large atomic units in dynamically scheduled machines
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11549468_58openalex-snapshot
Dynamic Partition of Memory Reference Instructions – A Register Guided Approach
inferred← citeshttps://doi.org/10.1007/11802839_29openalex-snapshot
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
inferred← citeshttps://doi.org/10.1007/3-540-44577-3_14openalex-snapshot
Microprocessors — 10 Years Back, 10 Years Ahead
inferred← citeshttps://doi.org/10.1007/3-540-57840-4_26openalex-snapshot
Increasing memory bandwidth for vector computations
inferred← citeshttps://doi.org/10.1007/978-3-319-09967-5_16openalex-snapshot
Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW Processors
inferred← citeshttps://doi.org/10.1007/978-3-540-27866-5_68openalex-snapshot
Contents Management in First-Level Multibanked Data Caches
inferred← citeshttps://doi.org/10.1007/978-3-540-45209-6_83openalex-snapshot
Counteracting Bank Misprediction in Sliced First-Level Caches
inferred← citeshttps://doi.org/10.1007/978-3-540-73625-7_29openalex-snapshot
Parallel Memory Architecture for TTA Processor
inferred← citeshttps://doi.org/10.1007/978-3-642-24568-8_1openalex-snapshot
A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/bf03356750openalex-snapshot
A Mean Value Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques
inferred← citeshttps://doi.org/10.1007/bfb0020457openalex-snapshot
Bounds on memory bandwidth in streamed computations
inferred← citeshttps://doi.org/10.1007/bfb0100700openalex-snapshot
Reducing memory traffic via redundant store instructions
inferred← citeshttps://doi.org/10.1007/s11265-008-0173-yopenalex-snapshot
Parallel Memory Architecture for Application-Specific Instruction-Set Processors
inferred← citeshttps://doi.org/10.1007/s11554-008-0082-0openalex-snapshot
Custom parallel caching schemes for hardware-accelerated image compression
inferred← citeshttps://doi.org/10.1016/j.mejo.2012.05.001openalex-snapshot
FPGA based efficient on-chip memory for image processing algorithms
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.12.007openalex-snapshot
System implications of LLC MSHRs in scalable memory systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2009.09.002openalex-snapshot
Access region cache with register guided memory reference partitioning
inferred← citeshttps://doi.org/10.1016/j.sysarc.2010.05.007openalex-snapshot
Multi-port abstraction layer for FPGA intensive memory exploitation applications
inferred← citeshttps://doi.org/10.1016/s0141-9331(02)00107-2openalex-snapshot
A scalable multi-porting solution for future wide-issue processors
inferred← citeshttps://doi.org/10.1080/02533839.1998.9670391openalex-snapshot
Exploring the design space of cache memories, bus width, and burst transfer memory systems
inferred← citeshttps://doi.org/10.1093/ietele/e90-c.11.2157openalex-snapshot
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words
inferred← citeshttps://doi.org/10.1109/12.752659openalex-snapshot
Effects of multithreading on cache performance
inferred← citeshttps://doi.org/10.1109/12.795219openalex-snapshot
The superthreaded processor architecture
inferred← citeshttps://doi.org/10.1109/12.811113openalex-snapshot
Active management of data caches by exploiting reuse information
inferred← citeshttps://doi.org/10.1109/12.919276openalex-snapshot
High bandwidth on-chip cache design
inferred← citeshttps://doi.org/10.1109/12.936237openalex-snapshot
A high-bandwidth memory pipeline for wide issue processors
inferred← citeshttps://doi.org/10.1109/12.956093openalex-snapshot
Improving latency tolerance of multithreading through decoupling
inferred← citeshttps://doi.org/10.1109/2.84896openalex-snapshot
Computer technology and architecture: an evolving interaction
inferred← citeshttps://doi.org/10.1109/40.621209openalex-snapshot
Simultaneous multithreading: a platform for next-generation processors
inferred← citeshttps://doi.org/10.1109/5.476078openalex-snapshot
The microarchitecture of superscalar processors
inferred← citeshttps://doi.org/10.1109/5.964438openalex-snapshot
Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling
inferred← citeshttps://doi.org/10.1109/88.218177openalex-snapshot
Optimizing a superscalar machine to run vector code
inferred← citeshttps://doi.org/10.1109/apccas.2006.342421openalex-snapshot
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline
inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420550openalex-snapshot
NBCache: An Efficient and Scalable Non-Blocking Cache for Coherent Multi-Chiplet Systems
inferred← citeshttps://doi.org/10.1109/eeis.1996.566916openalex-snapshot
Implementation and bandwidth considerations in multi ported, on chip data cache
inferred← citeshttps://doi.org/10.1109/eurmic.1998.711813openalex-snapshot
The latency hiding effectiveness of decoupled access/execute processors
inferred← citeshttps://doi.org/10.1109/hicss.1993.270688openalex-snapshot
Architectural resource requirements of contemporary benchmarks: a wish list
inferred← citeshttps://doi.org/10.1109/hicss.1994.323142openalex-snapshot
Experimental implementation of dynamic access ordering
inferred← citeshttps://doi.org/10.1109/hicss.1994.323156openalex-snapshot
Evaluation of pseudo vector processor based on slide-windowed registers
inferred← citeshttps://doi.org/10.1109/hicss.1994.323171openalex-snapshot
Accelerating architectural simulation by parallel execution of trace samples
inferred← citeshttps://doi.org/10.1109/hpca.1995.386526openalex-snapshot
Program balance and its impact on high performance RISC architectures
inferred← citeshttps://doi.org/10.1109/hpca.1995.386537openalex-snapshot
Access ordering and memory-conscious cache utilization
inferred← citeshttps://doi.org/10.1109/hpca.1995.386553openalex-snapshot
How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors?
inferred← citeshttps://doi.org/10.1109/hpca.1997.569691openalex-snapshot
A framework for statistical modeling of superscalar processor performance
inferred← citeshttps://doi.org/10.1109/hpca.1998.650543openalex-snapshot
Performance study of a concurrent multithreaded processor
inferred← citeshttps://doi.org/10.1109/hpca.1998.650559openalex-snapshot
Speculative versioning cache
inferred← citeshttps://doi.org/10.1109/hpca.2003.1183548openalex-snapshot
Just say no: benefits of early cache miss determination
inferred← citeshttps://doi.org/10.1109/hpca.2004.10003openalex-snapshot
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors
inferred← citeshttps://doi.org/10.1109/hprcta.2010.5670797openalex-snapshot
Comparative analysis of HPC and accelerator devices: Computation, memory, I/O, and power
inferred← citeshttps://doi.org/10.1109/icccas.2005.1495232openalex-snapshot
An efficient address mapping method for the shared multi-port cache in raid
inferred← citeshttps://doi.org/10.1109/iccd.1993.393409openalex-snapshot
A split data cache for superscalar processors
inferred← citeshttps://doi.org/10.1109/iccd.1995.528797openalex-snapshot
A superscalar RISC processor with pseudo vector processing feature
inferred← citeshttps://doi.org/10.1109/iccd.1997.628917openalex-snapshot
On effective data supply for multi-issue processors
inferred← citeshttps://doi.org/10.1109/iccd.1998.727076openalex-snapshot
Evaluating the performance of active cache management schemes
inferred← citeshttps://doi.org/10.1109/iccd.2001.955042openalex-snapshot
Access region cache: a multi-porting solution for future wide-issue processors
inferred← citeshttps://doi.org/10.1109/iccd.2006.4380858openalex-snapshot
Design and Implementation of the TRIPS Primary Memory System
inferred← citeshttps://doi.org/10.1109/icpp.1993.85openalex-snapshot
Exploiting Spatial and Temporal Parallelism in the Multithreaded Node Architecture Implemented on Superscalar RISC Processors
inferred← citeshttps://doi.org/10.1109/icpp.1994.130openalex-snapshot
Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories
inferred← citeshttps://doi.org/10.1109/ipps.1996.508052openalex-snapshot
A memory controller for improved performance of streamed computations on symmetric multiprocessors
inferred← citeshttps://doi.org/10.1109/isca.1992.753304openalex-snapshot
The Expandable Split Window Paradigm for Exploiting Fine-grain Parallelism
inferred← citeshttps://doi.org/10.1109/isca.1993.698560openalex-snapshot
Cache Write Policies And Performance
inferred← citeshttps://doi.org/10.1109/isca.1993.698568openalex-snapshot
Limitations Of Cache Prefetching On A Bus-based Multiprocessor
inferred← citeshttps://doi.org/10.1109/isca.1994.288148openalex-snapshot
Complexity/performance tradeoffs with non-blocking loads
inferred← citeshttps://doi.org/10.1109/isca.1994.288152openalex-snapshot
Exploring the design space for a shared-cache multiprocessor
inferred← citeshttps://doi.org/10.1109/isca.1994.288163openalex-snapshot
Tradeoffs in two-level on-chip caching
inferred← citeshttps://doi.org/10.1109/isca.1999.765943openalex-snapshot
Decoupling local variable accesses in a wide-issue superscalar processor
inferred← citeshttps://doi.org/10.1109/isca.2001.937443openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferred← citeshttps://doi.org/10.1109/isca.2004.1310762openalex-snapshot
Wire delay is not a problem for SMT (in the near future)
inferred← citeshttps://doi.org/10.1109/isca.2005.47openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferred← citeshttps://doi.org/10.1109/isca.2008.15openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferred← citeshttps://doi.org/10.1109/isie.1994.333088openalex-snapshot
A concurrent hardware software management scheme for memory hierarchies
inferred← citeshttps://doi.org/10.1109/jproc.2004.837627openalex-snapshot
Decisive aspects in the evolution of microprocessors
inferred← citeshttps://doi.org/10.1109/l-ca.2002.2openalex-snapshot
An Address Transformation Combining Block- and Word-Int erleaving
inferred← citeshttps://doi.org/10.1109/mascot.1996.500991openalex-snapshot
The inaccuracy of trace-driven simulation using incomplete multiprogramming trace data
inferred← citeshttps://doi.org/10.1109/micro.1992.697018openalex-snapshot
Tradeoffs In Processor/memory Interfaces For Superscalar Processors
inferred← citeshttps://doi.org/10.1109/micro.1993.282757openalex-snapshot
Speculative execution exception recovery using write-back suppression
inferred← citeshttps://doi.org/10.1109/micro.1993.282758openalex-snapshot
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors
inferred← citeshttps://doi.org/10.1109/micro.1995.476830openalex-snapshot
SPAID: software prefetching in pointer- and call-intensive environments
inferred← citeshttps://doi.org/10.1109/micro.1995.476832openalex-snapshot
Cache miss heuristics and preloading techniques for general-purpose programs
inferred← citeshttps://doi.org/10.1109/micro.1996.566463openalex-snapshot
Tango: a hardware-based data prefetching technique for superscalar processors
inferred← citeshttps://doi.org/10.1109/micro.1997.645796openalex-snapshot
On high-bandwidth data cache design for multi-issue processors
inferred← citeshttps://doi.org/10.1109/micro.1997.645814openalex-snapshot
Streamlining inter-operation memory communication via data dependence prediction
inferred← citeshttps://doi.org/10.1109/micro.1999.809451openalex-snapshot
Access region locality for high-bandwidth processor memory system design
inferred← citeshttps://doi.org/10.1109/micro.2001.991122openalex-snapshot
Reducing the complexity of the register file in dynamic superscalar processors
inferred← citeshttps://doi.org/10.1109/micro.2006.44openalex-snapshot
Scalable Cache Miss Handling for High Memory-Level Parallelism
inferred← citeshttps://doi.org/10.1109/mm.2003.1261393openalex-snapshot
Nonuniform cache architectures for wire-delay dominated on-chip caches
inferred← citeshttps://doi.org/10.1109/pact.1997.644009openalex-snapshot
Improving the memory bandwidth of highly-integrated, wide-issue, microprocessor-based systems
inferred← citeshttps://doi.org/10.1109/pact.1998.727137openalex-snapshot
Optical versus electronic bus for address-transactions in future SMP architectures
inferred← citeshttps://doi.org/10.1109/spdp.1996.570325openalex-snapshot
Improving the parallelism and concurrency in decoupled architectures
inferred← citeshttps://doi.org/10.1109/superc.1992.236638openalex-snapshot
Pseudo vector processor based on register-windowed superscalar pipeline
inferred← citeshttps://doi.org/10.1109/tc.2009.57openalex-snapshot
Store Buffer Design for Multibanked Data Caches
inferred← citeshttps://doi.org/10.1109/tencon.1994.369318openalex-snapshot
A compile time data management algorithm
inferred← citeshttps://doi.org/10.1109/tpds.2007.1091openalex-snapshot
A NUCA Substrate for Flexible CMP Cache Sharing
inferred← citeshttps://doi.org/10.1109/tron.1991.213102openalex-snapshot
Analysis of SPEC benchmark programs
inferred← citeshttps://doi.org/10.1109/wsc.2000.899754openalex-snapshot
Facilitating level three cache studies using set sampling
inferred← citeshttps://doi.org/10.1145/1028176.1006706openalex-snapshot
Wire Delay is Not a Problem for SMT (In the Near Future)
inferred← citeshttps://doi.org/10.1145/1080695.1070009openalex-snapshot
Store Buffer Design in First-Level Multibanked Data Caches
inferred← citeshttps://doi.org/10.1145/1088149.1088154openalex-snapshot
A NUCA substrate for flexible CMP cache sharing
inferred← citeshttps://doi.org/10.1145/1101868.1101880openalex-snapshot
Exploiting the replication cache to improve performance for multiple-issue microprocessors
inferred← citeshttps://doi.org/10.1145/1147349.1147356openalex-snapshot
Exploiting the replication cache to improve cache read bandwidth cost effectively
inferred← citeshttps://doi.org/10.1145/1228784.1228794openalex-snapshot
I-cache multi-banking and vertical interleaving
inferred← citeshttps://doi.org/10.1145/123465.123472openalex-snapshot
The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling
inferred← citeshttps://doi.org/10.1145/123465.123478openalex-snapshot
Data access microarchitectures for superscalar processors with compiler-assisted data prefetching
inferred← citeshttps://doi.org/10.1145/125826.125941openalex-snapshot
Delayed consistency and its effects on the miss rate of parallel programs
inferred← citeshttps://doi.org/10.1145/1394608.1382159openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferred← citeshttps://doi.org/10.1145/139669.139703openalex-snapshot
The expandable split window paradigm for exploiting fine-grain parallelsim
inferred← citeshttps://doi.org/10.1145/143365.143486openalex-snapshot
Reducing memory latency via non-blocking and prefetching caches
inferred← citeshttps://doi.org/10.1145/143371.143486openalex-snapshot
Reducing memory latency via non-blocking and prefetching caches
inferred← citeshttps://doi.org/10.1145/144965.145804openalex-snapshot
Tradeoffs in processor/memory interfaces for superscalar processors
inferred← citeshttps://doi.org/10.1145/146628.139703openalex-snapshot
The expandable split window paradigm for exploiting fine-grain parallelism
inferred← citeshttps://doi.org/10.1145/165123.165154openalex-snapshot
Cache write policies and performance
inferred← citeshttps://doi.org/10.1145/165123.165163openalex-snapshot
Limitations of cache prefetching on a bus-based multiprocessor
inferred← citeshttps://doi.org/10.1145/165939.165998openalex-snapshot
A scalar architecture for pseudo vector processing based on slide-windowed registers
inferred← citeshttps://doi.org/10.1145/173682.165154openalex-snapshot
Cache write policies and performance
inferred← citeshttps://doi.org/10.1145/173682.165163openalex-snapshot
Limitations of cache prefetching on a bus-based multiprocessor
inferred← citeshttps://doi.org/10.1145/1862648.1862649openalex-snapshot
Characterization of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration
inferred← citeshttps://doi.org/10.1145/191995.192026openalex-snapshot
Exploring the design space for a shared-cache multiprocessor
inferred← citeshttps://doi.org/10.1145/191995.192029openalex-snapshot
Complexity/performance tradeoffs with non-blocking loads
inferred← citeshttps://doi.org/10.1145/192007.192015openalex-snapshot
Tradeoffs in two-level on-chip caching
inferred← citeshttps://doi.org/10.1145/192007.192026openalex-snapshot
Exploring the design space for a shared-cache multiprocessor
inferred← citeshttps://doi.org/10.1145/192007.192029openalex-snapshot
Complexity/performance tradeoffs with non-blocking loads
inferred← citeshttps://doi.org/10.1145/1967677.1967699openalex-snapshot
An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures
inferred← citeshttps://doi.org/10.1145/200912.201006openalex-snapshot
Effective cache prefetching on bus-based multiprocessors
inferred← citeshttps://doi.org/10.1145/2016603.1967699openalex-snapshot
An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures
inferred← citeshttps://doi.org/10.1145/224170.224397openalex-snapshot
The benefits of clustering in shared address space multiprocessors
inferred← citeshttps://doi.org/10.1145/232973.232983openalex-snapshot
Memory bandwidth limitations of future microprocessors
inferred← citeshttps://doi.org/10.1145/232973.232989openalex-snapshot
Increasing cache port efficiency for dynamic superscalar microprocessors
inferred← citeshttps://doi.org/10.1145/232973.232990openalex-snapshot
High-bandwidth address translation for multiple-issue processors
inferred← citeshttps://doi.org/10.1145/232974.232983openalex-snapshot
Memory bandwidth limitations of future microprocessors
inferred← citeshttps://doi.org/10.1145/232974.232989openalex-snapshot
Increasing cache port efficiency for dynamic superscalar microprocessors
inferred← citeshttps://doi.org/10.1145/232974.232990openalex-snapshot
High-bandwidth address translation for multiple-issue processors
inferred← citeshttps://doi.org/10.1145/237090.237140openalex-snapshot
The case for a single-chip multiprocessor
inferred← citeshttps://doi.org/10.1145/237578.237635openalex-snapshot
Improving single-process performance with multithreaded processors
inferred← citeshttps://doi.org/10.1145/242694.246990openalex-snapshot
Constructing instruction traces from cache-filtered address traces (CITCAT)
inferred← citeshttps://doi.org/10.1145/248208.237140openalex-snapshot
The case for a single-chip multiprocessor
inferred← citeshttps://doi.org/10.1145/248209.237140openalex-snapshot
The case for a single-chip multiprocessor
inferred← citeshttps://doi.org/10.1145/263580.263585openalex-snapshot
Increasing memory bandwidth with wide buses
inferred← citeshttps://doi.org/10.1145/263580.263595openalex-snapshot
Data caches for superscalar processors
inferred← citeshttps://doi.org/10.1145/264107.264152openalex-snapshot
The design and analysis of a cache architecture for texture mapping
inferred← citeshttps://doi.org/10.1145/264107.264153openalex-snapshot
Designing high bandwidth on-chip caches
inferred← citeshttps://doi.org/10.1145/264107.264201openalex-snapshot
Complexity-effective superscalar processors
inferred← citeshttps://doi.org/10.1145/264107.264213openalex-snapshot
Run-time adaptive cache hierarchy management via reference analysis
inferred← citeshttps://doi.org/10.1145/277830.277938openalex-snapshot
Resource widening versus replication
inferred← citeshttps://doi.org/10.1145/277830.277941openalex-snapshot
Utilizing reuse information in data cache management
inferred← citeshttps://doi.org/10.1145/285930.285952openalex-snapshot
Retrospective: instruction issue logic for high-performance, interruptable pipelined processors
inferred← citeshttps://doi.org/10.1145/2888401openalex-snapshot
Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization Metrics
inferred← citeshttps://doi.org/10.1145/298151.298422openalex-snapshot
A dynamic scheduling logic for exploiting multiple functional units in single chip multithreaded architectures
inferred← citeshttps://doi.org/10.1145/307338.300988openalex-snapshot
Decoupling local variable accesses in a wide-issue superscalar processor
inferred← citeshttps://doi.org/10.1145/3314221.3314599openalex-snapshot
Co-optimizing memory-level parallelism and cache-level parallelism
inferred← citeshttps://doi.org/10.1145/335231.335257openalex-snapshot
Hardware spatial forwarding for widely shared data
inferred← citeshttps://doi.org/10.1145/379240.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferred← citeshttps://doi.org/10.1145/384285.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferred← citeshttps://doi.org/10.1145/384286.264152openalex-snapshot
The design and analysis of a cache architecture for texture mapping
inferred← citeshttps://doi.org/10.1145/384286.264153openalex-snapshot
Designing high bandwidth on-chip caches
inferred← citeshttps://doi.org/10.1145/384286.264213openalex-snapshot
Run-time adaptive cache hierarchy management via reference analysis
inferred← citeshttps://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferred← citeshttps://doi.org/10.1145/605432.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferred← citeshttps://doi.org/10.1145/635506.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferred← citeshttps://doi.org/10.1145/635508.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferred← citeshttps://doi.org/10.1147/rd.374.0547openalex-snapshot
A load-instruction unit for pipelined processors
inferred← citeshttps://doi.org/10.18130/v3rn2fopenalex-snapshot
Hardware Support for Dynamic Access Ordering: Performance of Some Design Options
inferred← citeshttps://doi.org/10.5445/ir/1000015825openalex-snapshot
Task Activity Vectors: A Novel Metric for Temperature-Aware and Energy-Efficient Scheduling
inferred← citeshttps://doi.org/10.5555/147877.148106openalex-snapshot
Pseudo vector processor based on register-windowed superscalar pipeline
inferred← citeshttps://doi.org/10.5555/224659.224725openalex-snapshot
An analytical model of high performance superscalar-based multiprocessors
inferred← citeshttps://doi.org/10.5555/224659.224951openalex-snapshot
Increasing cache bandwidth using multi-port caches for exploiting ILP in non-numerical code
inferred← citeshttps://doi.org/10.5555/225160.225197openalex-snapshot
SPAID: software prefetching in pointer- and call-intensive environments
inferred← citeshttps://doi.org/10.5555/225160.225199openalex-snapshot
Cache miss heuristics and preloading techniques for general-purpose programs
inferred← citeshttps://doi.org/10.5555/255235.255250openalex-snapshot
Two-ported cache alternatives for superscalar processors
inferred← citeshttps://doi.org/10.5555/255235.255251openalex-snapshot
A study on the number of memory ports in multiple instruction issue machines
inferred← citeshttps://doi.org/10.5555/255235.255293openalex-snapshot
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors
inferred← citeshttps://doi.org/10.5555/266800.266805openalex-snapshot
On high-bandwidth data cache design for multi-issue processors
inferred← citeshttps://doi.org/10.5555/266800.266823openalex-snapshot
Streamlining inter-operation memory communication via data dependence prediction
inferred← citeshttps://doi.org/10.5555/320080.320101openalex-snapshot
Access region locality for high-bandwidth processor memory system design
inferred← citeshttps://doi.org/10.5555/510378.510451openalex-snapshot
Facilitating level three cache studies using set sampling
inferred← citeshttps://doi.org/10.5555/522344.825682openalex-snapshot
Optical Bus versus Electronic Bus for Address-Transactions in Future SMP Architectures
inferred← citeshttps://doi.org/10.5555/522659.825646openalex-snapshot
Improving the memory bandwidth of highly-integrated, wide-issue, microprocessor-based systems
inferred← citeshttps://doi.org/10.5555/563998.564029openalex-snapshot
Reducing the complexity of the register file in dynamic superscalar processors
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.