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Array data flow analysis for load-store optimizations in superscalar architectures

https://doi.org/10.1007/bfb0014188
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/spe.4380240104openalex-snapshot
Scalar replacement in the presence of conditional control flow
inferredcites →https://doi.org/10.1007/3-540-55984-1_17openalex-snapshot
A register allocation framework based on hierarchical cyclic interval graphs
inferredcites →https://doi.org/10.1007/3-540-55984-1_18openalex-snapshot
Register pipelining: An integrated approach to register allocation for scalar and subscripted variables
inferredcites →https://doi.org/10.1007/bf01379099openalex-snapshot
Data dependence and its application to parallel processing
inferredcites →https://doi.org/10.1057/jors.1991.155openalex-snapshot
Introduction to Algorithms
inferredcites →https://doi.org/10.1145/103135.214520openalex-snapshot
Practical adaption of the global optimization algorithm of Morel and Renvoise
inferredcites →https://doi.org/10.1145/106972.106987openalex-snapshot
Code generation for streaming: an access/execute mechanism
inferredcites →https://doi.org/10.1145/106974.106987openalex-snapshot
Code generation for streaming: an access/execute mechanism
inferredcites →https://doi.org/10.1145/143095.143135openalex-snapshot
How to analyze large programs efficiently and informatively
inferredcites →https://doi.org/10.1145/143165.143216openalex-snapshot
Generalized dominators and post-dominators
inferredcites →https://doi.org/10.1145/155090.155097openalex-snapshot
A practical data flow framework for array reference analysis and its use in optimizations
inferredcites →https://doi.org/10.1145/155090.155116openalex-snapshot
Load/store range analysis for global register allocation
inferredcites →https://doi.org/10.1145/173262.155116openalex-snapshot
Load/store range analysis for global register allocation
inferredcites →https://doi.org/10.1145/183432.183443openalex-snapshot
Optimal code motion
inferredcites →https://doi.org/10.1145/359060.359069openalex-snapshot
Global optimization by suppression of partial redundancies
inferredcites →https://doi.org/10.1145/68182.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1145/70082.68185openalex-snapshot
Overlapped loop support in the Cydra 5
inferredcites →https://doi.org/10.1145/800230.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/872726.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/93542.93553openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1145/989393.989403openalex-snapshot
Register allocation and spilling via graph coloring
inferredcites →https://doi.org/10.1145/989393.989428openalex-snapshot
Improving register allocation for subscripted variables

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/spe.546openalex-snapshot
An experimental evaluation of scalar replacement on scientific benchmarks
inferred← citeshttps://doi.org/10.1002/spe.604openalex-snapshot
Partial redundancy elimination for access expressions by speculative code motion
inferred← citeshttps://doi.org/10.1007/3-540-46423-9_10openalex-snapshot
A Framework for Loop Distribution on Limited On-Chip Memory Processors
inferred← citeshttps://doi.org/10.1007/3-540-48319-5_18openalex-snapshot
Copy Elimination for Parallelizing Compilers
inferred← citeshttps://doi.org/10.1007/978-3-540-45099-3_9openalex-snapshot
Unified Analysis of Array and Object References in Strongly Typed Languages
inferred← citeshttps://doi.org/10.1007/978-3-642-54807-9_3openalex-snapshot
Inter-iteration Scalar Replacement Using Array SSA Form
inferred← citeshttps://doi.org/10.1007/bfb0026433openalex-snapshot
A new fast algorithm for optimal register allocation in modulo scheduled loops
inferred← citeshttps://doi.org/10.1016/s0026-2692(03)00169-1openalex-snapshot
Address register allocation for arrays in loops of embedded programs
inferred← citeshttps://doi.org/10.1109/hipc.1997.634517openalex-snapshot
Code optimization as a side effect of instruction scheduling
inferred← citeshttps://doi.org/10.1109/iccl.1998.674173openalex-snapshot
Path profile guided partial redundancy elimination using speculation
inferred← citeshttps://doi.org/10.1109/icpp.2000.876075openalex-snapshot
Load redundancy removal through instruction reuse
inferred← citeshttps://doi.org/10.1109/micro.1997.645834openalex-snapshot
Resource-sensitive profile-directed data flow analysis for code optimization
inferred← citeshttps://doi.org/10.1109/pact.1997.644007openalex-snapshot
Path profile guided partial dead code elimination using predication
inferred← citeshttps://doi.org/10.1109/tc.2002.1039852openalex-snapshot
Loop restructuring for data I/O minimization on limited on-chip memory embedded processors
inferred← citeshttps://doi.org/10.1145/268946.268956openalex-snapshot
Array SSA form and its use in parallelization
inferred← citeshttps://doi.org/10.1145/544536.544542openalex-snapshot
Global array reference allocation
inferred← citeshttps://doi.org/10.47749/t/unicamp.2002.275878openalex-snapshot
Alocação global de registradores de endereçamento para referencias a vetores em DSPs
inferred← citeshttps://doi.org/10.5555/266800.266836openalex-snapshot
Resource-sensitive profile-directed data flow analysis for code optimization
inferred← citeshttps://doi.org/10.5555/522659.825652openalex-snapshot
Path profile guided partial dead code elimination using predication
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