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Code generation for streaming: an access/execute mechanism

https://doi.org/10.1145/106972.106987
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1145/327070.327117openalex-snapshot
PIPE
inferredcites →https://doi.org/10.1145/357401.357403openalex-snapshot
Decoupled access/execute computer architectures
inferredcites →https://doi.org/10.1145/36177.36203openalex-snapshot
The ZS-1 central processor
inferredcites →https://doi.org/10.1145/44571.44577openalex-snapshot
The WM computer architecture
inferredcites →https://doi.org/10.1145/800050.801824openalex-snapshot
The 801 minicomputer
inferredcites →https://doi.org/10.1145/800230.806977openalex-snapshot
An overview of the PL.8 compiler
inferredcites →https://doi.org/10.1145/960116.54023openalex-snapshot
A portable global optimizer and linker
inferredcites →https://doi.org/10.1147/rd.341.0023openalex-snapshot
IBM RISC System/6000 processor architecture
inferredcites →https://doi.org/10.1184/r1/6610535openalex-snapshot
The design of an optimizing compiler
inferredcites →https://doi.org/10.18130/v35j58openalex-snapshot
The WM Family of computer Architectures
inferredcites →https://doi.org/10.18130/v3w77fopenalex-snapshot
The WM Computer Architectures Principles of Operation

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Register pipelining: An integrated approach to register allocation for scalar and subscripted variables
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Some design aspects for VLIW architectures exploiting fine-grained parallelism
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Increasing memory bandwidth for vector computations
inferred← citeshttps://doi.org/10.1007/3-540-57840-4_27openalex-snapshot
The advantages of machine-dependent global optimization
inferred← citeshttps://doi.org/10.1007/3-540-57877-3_23openalex-snapshot
A practical approach to the symbolic debugging of parallelized code
inferred← citeshttps://doi.org/10.1007/bf02577734openalex-snapshot
Code scheduling for multiple instruction stream architectures
inferred← citeshttps://doi.org/10.1007/bf03356757openalex-snapshot
Array Data Flow Analysis for Load-Store Optimizations in Fine-Grain Architectures
inferred← citeshttps://doi.org/10.1007/bfb0014188openalex-snapshot
Array data flow analysis for load-store optimizations in superscalar architectures
inferred← citeshttps://doi.org/10.1007/bfb0020457openalex-snapshot
Bounds on memory bandwidth in streamed computations
inferred← citeshttps://doi.org/10.1016/j.parco.2008.11.004openalex-snapshot
Efficient compilation for queue size constrained queue processors
inferred← citeshttps://doi.org/10.1023/a:1018792002672openalex-snapshot
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors1
inferred← citeshttps://doi.org/10.1080/01495739708941419openalex-snapshot
THE EFFICIENT CREATION OF SINGLE ASSIGNMENT FORMS FROM UNSTRUCTURED CODE*
inferred← citeshttps://doi.org/10.1109/12.895941openalex-snapshot
Dynamic access ordering for streamed computations
inferred← citeshttps://doi.org/10.1109/2.689677openalex-snapshot
Smarter memory: improving bandwidth for streamed references
inferred← citeshttps://doi.org/10.1109/hicss.1993.270618openalex-snapshot
Memory bandwidth optimizations for wide-bus machines
inferred← citeshttps://doi.org/10.1109/hicss.1994.323142openalex-snapshot
Experimental implementation of dynamic access ordering
inferred← citeshttps://doi.org/10.1109/hicss.1996.495465openalex-snapshot
An efficient algorithm for the creation of single assignment forms
inferred← citeshttps://doi.org/10.1109/hpca.1995.386537openalex-snapshot
Access ordering and memory-conscious cache utilization
inferred← citeshttps://doi.org/10.1109/hpca.1999.744337openalex-snapshot
Access order and effective bandwidth for streams on a Direct Rambus memory
inferred← citeshttps://doi.org/10.1109/hpca.2000.824337openalex-snapshot
Design of a parallel vector access unit for SDRAM memory systems
inferred← citeshttps://doi.org/10.1109/icpp.1994.57openalex-snapshot
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors
inferred← citeshttps://doi.org/10.1109/ipps.1996.508052openalex-snapshot
A memory controller for improved performance of streamed computations on symmetric multiprocessors
inferred← citeshttps://doi.org/10.1109/isca.1992.753334openalex-snapshot
Evaluation of the WM Architecture
inferred← citeshttps://doi.org/10.1109/ishls.1994.302339openalex-snapshot
An integrated approach to retargetable code generation
inferred← citeshttps://doi.org/10.1109/micro.1992.697016openalex-snapshot
Misc: A Multiple Instruction Stream Computer
inferred← citeshttps://doi.org/10.1109/micro.1993.282749openalex-snapshot
Techniques for extracting instruction level parallelism on MIMD architectures
inferred← citeshttps://doi.org/10.1109/micro.2005.13openalex-snapshot
Automatic Thread Extraction with Decoupled Software Pipelining
inferred← citeshttps://doi.org/10.1145/1013235.1013255openalex-snapshot
Design and implementation of correlating caches
inferred← citeshttps://doi.org/10.1145/1048935.1050199openalex-snapshot
Identifying and Exploiting Spatial Regularity in Data Memory References
inferred← citeshttps://doi.org/10.1145/139669.140402openalex-snapshot
Evaluation of the WM architecture
inferred← citeshttps://doi.org/10.1145/144965.145800openalex-snapshot
MISC
inferred← citeshttps://doi.org/10.1145/146628.140402openalex-snapshot
Evaluation of the WM architecture
inferred← citeshttps://doi.org/10.1145/178243.178259openalex-snapshot
Memory access coalescing
inferred← citeshttps://doi.org/10.1145/237578.237594openalex-snapshot
Design and evaluation of dynamic access ordering hardware
inferred← citeshttps://doi.org/10.1145/335231.335247openalex-snapshot
Hardware-only stream prefetching and dynamic access ordering
inferred← citeshttps://doi.org/10.1145/581630.581647openalex-snapshot
Increasing power efficiency of multi-core network processors through data filtering
inferred← citeshttps://doi.org/10.1145/773473.178259openalex-snapshot
Memory access coalescing
inferred← citeshttps://doi.org/10.18130/v31r1kopenalex-snapshot
Data Cache Performance When Vector-Like Accesses Bypass the Cache
inferred← citeshttps://doi.org/10.18130/v37n35openalex-snapshot
Access Ordering and Effective Memory Bandwidth
inferred← citeshttps://doi.org/10.18130/v3df6sopenalex-snapshot
Access Ordering Algorithms for a Single Module Memory
inferred← citeshttps://doi.org/10.18130/v3fc6dopenalex-snapshot
Maximizing Memory Bandwidth for Streamed Computations
inferred← citeshttps://doi.org/10.18130/v3k17kopenalex-snapshot
Dynamic Access Ordering: Bounds on Memory Bandwidth
inferred← citeshttps://doi.org/10.18130/v3nn14openalex-snapshot
Evaluation of Dynamic Access Ordering Hardware
inferred← citeshttps://doi.org/10.18130/v3nz17openalex-snapshot
Access Ordering Algorithms for a Multicopy Memory
inferred← citeshttps://doi.org/10.18130/v3rn2fopenalex-snapshot
Hardware Support for Dynamic Access Ordering: Performance of Some Design Options
inferred← citeshttps://doi.org/10.18130/v3xf6fopenalex-snapshot
Access Ordering Algorithms for an Interleaved Memory
inferred← citeshttps://doi.org/10.2172/15004542openalex-snapshot
Memory System Technologies for Future High-End Computing Systems
inferred← citeshttps://doi.org/10.5555/224659.224712openalex-snapshot
Practical approach to single assignment code
inferred← citeshttps://doi.org/10.5555/254208.254233openalex-snapshot
An integrated approach to retargetable code generation
inferred← citeshttps://doi.org/10.5555/255235.255273openalex-snapshot
Techniques for extracting instruction level parallelism on MIMD architectures
inferred← citeshttps://doi.org/10.5753/sbac-pad.1994.21882openalex-snapshot
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