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Data-structures for the verification of timed automata
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Symbolic Model Checking for Real-Time Systems
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Timing assumptions and verification of finite-state concurrent systems
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Toupie=μ-calculus+constraints
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An automata-theoretic approach to Presburger arithmetic constraints
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Timing analysis of asynchronous circuits using timed automata
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Verification of an Audio Protocol with bus collision using Uppaal
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Verifying ET-LOTOS programs with KRONOS
inferredcites →https://doi.org/10.1016/0304-3975(94)90010-8openalex-snapshot
A theory of timed automata
inferredcites →https://doi.org/10.1109/cdc.1994.410933openalex-snapshot
Discretization of timed automata
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Automatic symbolic verification of embedded systems
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Graph-Based Algorithms for Boolean Function Manipulation
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Real-Time Symbolic Model Checking for Discrete Time Models
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Symbolic Verification of Complex Real-time Systems with Clock-restriction Diagram
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Symbolic Model Checking of Finite Precision Timed Automata
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On Sampled Semantics of Timed Systems
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Timed Verification of Asynchronous Circuits
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Efficient Verification of Timed Automata with BDD-Like Data-Structures
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On the Representation of Timed Polyhedra
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Improvements in BDD-Based Reachability Analysis of Timed Automata
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Efficient Timed Reachability Analysis Using Clock Difference Diagrams
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Using MTBDDs for Composition and Model Checking of Real-Time Systems
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Some progress in the symbolic verification of timed automata
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Model checking timed automata
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CMC: A Tool for Compositional Model-Checking of Real-Time Systems
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Trace Abstraction Refinement for Timed Automata
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Specification and Model Checking of Temporal Properties in Time Petri Nets and Timed Automata
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Toward Unbounded Model Checking for Region Automata
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Making Timed Automata Communicate
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Bounded Model Checking Real-Time Multi-agent Systems with Clock Differences: Theory and Implementation
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On discretization of delays in timed automata and digital circuits
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Fully Symbolic Model Checking of Timed Systems using Difference Decision Diagrams1 1This work was carried out while the authors were at the Department of Information Technology, Technical University of Denmark, and was finnancially supported by a grant from the Danish Technical Research Council.
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