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On discretization of delays in timed automata and digital circuits

https://doi.org/10.1007/bfb0055642
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1006/inco.1993.1024openalex-snapshot
Model-Checking in Dense Real-Time
inferredcites →https://doi.org/10.1006/inco.1994.1045openalex-snapshot
Symbolic Model Checking for Real-Time Systems
inferredcites →https://doi.org/10.1007/3-540-52148-8_17openalex-snapshot
Timing assumptions and verification of finite-state concurrent systems
inferredcites →https://doi.org/10.1007/3-540-55719-9_103openalex-snapshot
What good are digital clocks?
inferredcites →https://doi.org/10.1007/3-540-60385-9_12openalex-snapshot
Timing analysis of asynchronous circuits using timed automata
inferredcites →https://doi.org/10.1007/3-540-63166-6_19openalex-snapshot
Some progress in the symbolic verification of timed automata
inferredcites →https://doi.org/10.1007/3-540-63166-6_20openalex-snapshot
STARI: A case study in compositional and hierarchical timing verification
inferredcites →https://doi.org/10.1007/978-1-4612-4210-9openalex-snapshot
Asynchronous Circuits
inferredcites →https://doi.org/10.1007/bfb0014737openalex-snapshot
Data-structures for the verification of timed automata
inferredcites →https://doi.org/10.1007/bfb0020947openalex-snapshot
The tool Kronos
inferredcites →https://doi.org/10.1007/bfb0036202openalex-snapshot
From finite automata toward hybrid systems (Extended abstract)
inferredcites →https://doi.org/10.1016/0304-3975(94)90010-8openalex-snapshot
A theory of timed automata
inferredcites →https://doi.org/10.1109/cdc.1994.410933openalex-snapshot
Discretization of timed automata
inferredcites →https://doi.org/10.1109/iccsse.1996.554845openalex-snapshot
Hardware timing verification using KRONOS
inferredcites →https://doi.org/10.1109/lics.1990.113763openalex-snapshot
A logic of concrete time intervals

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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On Sampled Semantics of Timed Systems
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Approximation, Sampling and Voting in Hybrid Computing Systems
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Integrating Discrete- and Continuous-Time Metric Temporal Logics Through Sampling
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Universality and Language Inclusion for Open and Closed Timed Automata
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Improvements in BDD-Based Reachability Analysis of Timed Automata
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Extending Timed Automaton and Real-Time Logic to Many-Valued Reasoning
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Toward an Approximation Theory for Computerised Control
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Correct Hardware Design and Verification Methods
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Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics
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Tweaking the Odds in Probabilistic Timed Automata
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Memory Efficient Data Structures for Explicit Verification of Timed Systems
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Interval Abstraction Refinement for Model Checking of Timed-Arc Petri Nets
inferred← citeshttps://doi.org/10.1007/978-3-319-10575-8_29openalex-snapshot
Model Checking Real-Time Systems
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Scaling BDD-based Timed Verification with Simulation Reduction
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Model Checking for Probabilistic Timed Systems
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Can Decision Diagrams Overcome State Space Explosion in Real-Time Verification?
inferred← citeshttps://doi.org/10.1007/978-3-540-40903-8_9openalex-snapshot
Performance Analysis of Probabilistic Timed Automata Using Digital Clocks
inferred← citeshttps://doi.org/10.1007/978-3-540-71389-0_2openalex-snapshot
Sampled Universality of Timed Automata
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Improvements for the Symbolic Verification of Timed Automata
inferred← citeshttps://doi.org/10.1007/978-3-642-04081-8_6openalex-snapshot
Volume and Entropy of Regular Timed Languages: Discretization Approach
inferred← citeshttps://doi.org/10.1007/978-3-642-23217-6_6openalex-snapshot
Timed Automata Can Always Be Made Implementable
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Thin and Thick Timed Regular Languages
inferred← citeshttps://doi.org/10.1007/s001650300007openalex-snapshot
Probabilistic Model Checking of Deadline Properties in the IEEE 1394 FireWire Root Contention Protocol
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Requirements-Level Semantics and Model Checking of Object-Oriented Statecharts
inferred← citeshttps://doi.org/10.1007/s10207-004-0037-9openalex-snapshot
Automated analysis of timed security: a case study on web privacy
inferred← citeshttps://doi.org/10.1007/s10703-006-0005-2openalex-snapshot
Performance analysis of probabilistic timed automata using digital clocks
inferred← citeshttps://doi.org/10.1007/s10703-012-0177-xopenalex-snapshot
Model checking for probabilistic timed automata
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Parameter synthesis for hierarchical concurrent real-time systems
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A survey of timed automata for the development of real-time systems
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Shrinking timed automata
inferred← citeshttps://doi.org/10.1016/j.ic.2015.03.003openalex-snapshot
Entropy of regular timed languages
inferred← citeshttps://doi.org/10.1016/j.tcs.2010.09.003openalex-snapshot
Weak bisimulation for Probabilistic Timed Automata
inferred← citeshttps://doi.org/10.1016/s0020-0190(01)00288-5openalex-snapshot
A note on the verification of automata specifications of probabilistic real-time systems
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Incremental specification with SCTL/MUS-T: a case study
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Verification of Asynchronous Circuits using Timed Automata
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Model Checking Semi-Continuous Time Models Using BDDs
inferred← citeshttps://doi.org/10.1016/s1571-0661(05)80369-xopenalex-snapshot
Timed CSP = Closed Timed Automata1
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Modelling and analysis of broadcasting embedded control systems
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Parameter synthesis for hierarchical concurrent real-time systems
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Revisiting digitization, robustness, and decidability for timed automata
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Automated Verification of Continuous Time Systems by Discrete Temporal Induction
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Tool support for verifying UML activity diagrams
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Event order abstraction for parametric real-time system verification
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Especificación y Análisis de Sistemas de Tiempo Real en Teoría de Tipos
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Sampled Semantics of Timed Automata
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Supervisory control of timed automata
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Soundness of Timed-Arc Workflow Nets in Discrete and Continuous-Time Semantics
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A Note on Digitization of Real-Time Models and Logics
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Applications of the Differential Calculus in the Study of the Timed Automata: the Inertial Delay Buffer
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Towards a Mathematical Theory of the Delays of the Asynchronous Circuits
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Real Time Models of the Asynchronous Circuits: The Delay Theory
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Volumetry of timed languages and applications
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