On the public citation graph
The influence of key length on the area-time complexity of sorting
0 signed · 26 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-642-68402-9_12openalex-snapshot
On the Area Required by VLSI Circuits
inferredcites →https://doi.org/10.1016/0010-4485(85)90134-4openalex-snapshot
Computational aspects of VLSI
inferredcites →https://doi.org/10.1016/0020-0190(80)90010-1openalex-snapshot
The complexity of a VLSI adder
inferredcites →https://doi.org/10.1016/0020-0190(85)90062-6openalex-snapshot
The VLSI optimality of the aks sorting network
inferredcites →https://doi.org/10.1109/tc.1983.1676178openalex-snapshot
The VLSI Complexity of Sorting
inferredcites →https://doi.org/10.1109/tc.1983.1676221openalex-snapshot
A Combinatorial Limit to the Computing Power of VLSI Circuits
inferredcites →https://doi.org/10.1109/tc.1984.5009338openalex-snapshot
An Architecture for Bitonic Sorting with Optimal VLSI Performnance
inferredcites →https://doi.org/10.1109/tc.1985.5009385openalex-snapshot
Tight Bounds on the Complexity of Parallel Sorting
inferredcites →https://doi.org/10.1109/tc.1985.5009386openalex-snapshot
Minimum Storage Sorting Networks
inferredcites →https://doi.org/10.1145/322261.322269openalex-snapshot
The Area-Time Complexity of Binary Multiplication
inferredcites →https://doi.org/10.1145/800057.808666openalex-snapshot
A minimum area VLSI network for O(logn) time sorting
inferredcites →https://doi.org/10.1145/800141.804666openalex-snapshot
The chip complexity of binary arithmetic
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-18099-0_42openalex-snapshot
Area-time tradeoffs for selection
inferred← citeshttps://doi.org/10.1007/978-3-642-74135-7_1openalex-snapshot
SFB 124: VLSI-Entwurfsmethoden und Parallelität
inferred← citeshttps://doi.org/10.1007/bf01840437openalex-snapshot
Area-time lower-bound techniques with applications to sorting
inferred← citeshttps://doi.org/10.1016/0304-3975(91)90179-6openalex-snapshot
Area complexity of merging
inferred← citeshttps://doi.org/10.1109/acssc.1985.671481openalex-snapshot
Remarks On Sorting And Parallel Processing
inferred← citeshttps://doi.org/10.1109/sfcs.1985.39openalex-snapshot
On information flow and sorting : New upper and lower bounds for VLSI circuits
inferred← citeshttps://doi.org/10.1137/0219016openalex-snapshot
Characterization of Associative Operations with Prefix Circuits of Constant Depth and Linear Size
inferred← citeshttps://doi.org/10.1145/12130.12177openalex-snapshot
Aspects of information flow in VLSI circuits
inferred← citeshttps://doi.org/10.1145/28395.28442openalex-snapshot
Size-time complexity of Boolean networks for prefix computations
inferred← citeshttps://doi.org/10.1145/48014.48017openalex-snapshot
Optimal VLSI circuits for sorting
inferred← citeshttps://doi.org/10.1145/62044.62052openalex-snapshot
Size-time complexity of Boolean networks for prefix computations
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.