On the public citation graph
Area-time lower-bound techniques with applications to sorting
0 signed · 56 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-642-68402-9_12openalex-snapshot
On the Area Required by VLSI Circuits
inferredcites →https://doi.org/10.1007/bfb0015730openalex-snapshot
The influence of key length on the area-time complexity of sorting
inferredcites →https://doi.org/10.1016/0010-4485(85)90134-4openalex-snapshot
Computational aspects of VLSI
inferredcites →https://doi.org/10.1016/0020-0190(80)90010-1openalex-snapshot
The complexity of a VLSI adder
inferredcites →https://doi.org/10.1016/0020-0190(85)90062-6openalex-snapshot
The VLSI optimality of the aks sorting network
inferredcites →https://doi.org/10.1016/0022-0000(81)90029-5openalex-snapshot
Area—time tradeoffs for matrix multiplication and related problems in VLSI models
inferredcites →https://doi.org/10.1109/sfcs.1982.32openalex-snapshot
Optimal allocation of computational resources in VLSI
inferredcites →https://doi.org/10.1109/tc.1983.1676178openalex-snapshot
The VLSI Complexity of Sorting
inferredcites →https://doi.org/10.1109/tc.1984.5009338openalex-snapshot
An Architecture for Bitonic Sorting with Optimal VLSI Performnance
inferredcites →https://doi.org/10.1109/tc.1985.5009384openalex-snapshot
A Minimum Area VLSI Network for O(log n) Time Sorting
inferredcites →https://doi.org/10.1109/tc.1985.5009385openalex-snapshot
Tight Bounds on the Complexity of Parallel Sorting
inferredcites →https://doi.org/10.1109/tc.1985.5009386openalex-snapshot
Minimum Storage Sorting Networks
inferredcites →https://doi.org/10.1137/0214040openalex-snapshot
Solving Undirected Graph Problems on VLSI
inferredcites →https://doi.org/10.1145/2422.322421openalex-snapshot
Information Transfer in Distributed Computing with Applications to VLSI
inferredcites →https://doi.org/10.1145/322261.322269openalex-snapshot
The Area-Time Complexity of Binary Multiplication
inferredcites →https://doi.org/10.1145/62.70openalex-snapshot
The VLSI Complexity of Selected Graph Problems
inferredcites →https://doi.org/10.1145/800057.808666openalex-snapshot
A minimum area VLSI network for O(logn) time sorting
inferredcites →https://doi.org/10.1145/800076.802483openalex-snapshot
The entropic limitations on VLSI computations(Extended Abstract)
inferredcites →https://doi.org/10.1145/800135.804414openalex-snapshot
Some complexity questions related to distributive computing(Preliminary Report)
inferredcites →https://doi.org/10.1145/800141.804666openalex-snapshot
The chip complexity of binary arithmetic
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1006/jpdc.1995.1080openalex-snapshot
Horizons of Parallel Computation
inferred← citeshttps://doi.org/10.1007/11602569_41openalex-snapshot
The Potential of On-Chip Multiprocessing for QCD Machines
inferred← citeshttps://doi.org/10.1007/3-540-16766-8_6openalex-snapshot
Optimal tradeoffs for addition on systolic arrays
inferred← citeshttps://doi.org/10.1007/3-540-18099-0_42openalex-snapshot
Area-time tradeoffs for selection
inferred← citeshttps://doi.org/10.1007/3-540-56320-2_57openalex-snapshot
Horizons of parallel computation
inferred← citeshttps://doi.org/10.1007/3-540-60220-8_46openalex-snapshot
Lower bounds to processor-time tradeoffs under bounded-speed message propagation
inferred← citeshttps://doi.org/10.1007/978-1-4615-3996-4_1openalex-snapshot
Parallel Architectures For Iterative Image Restoration
inferred← citeshttps://doi.org/10.1007/978-3-642-04128-0_47openalex-snapshot
On the Expansion and Diameter of Bluetooth-Like Topologies
inferred← citeshttps://doi.org/10.1007/bf01840352openalex-snapshot
On problem transformability in VLSI
inferred← citeshttps://doi.org/10.1007/bf02575818openalex-snapshot
On the VLSI complexity of some arithmetic and numerical problems
inferred← citeshttps://doi.org/10.1007/s00224-012-9390-7openalex-snapshot
On the Expansion and Diameter of Bluetooth-Like Topologies
inferred← citeshttps://doi.org/10.1007/s002240000066openalex-snapshot
Processor—Time Tradeoffs under Bounded-Speed Message Propagation: Part I, Upper Bounds
inferred← citeshttps://doi.org/10.1016/0020-0190(87)90218-3openalex-snapshot
The area-time complexity of the VLSI counter
inferred← citeshttps://doi.org/10.1016/0020-0190(90)90228-popenalex-snapshot
The area-time complexity of the greatest common divisor problem: a lower bound
inferred← citeshttps://doi.org/10.1016/0020-0190(91)90033-eopenalex-snapshot
Semelectivity is not sufficient
inferred← citeshttps://doi.org/10.1016/0304-3975(91)90179-6openalex-snapshot
Area complexity of merging
inferred← citeshttps://doi.org/10.1051/ita/1995290605091openalex-snapshot
Cutwidth of the de Bruijn graph
inferred← citeshttps://doi.org/10.1109/12.238486openalex-snapshot
On the lower bound to the VLSI complexity of number conversion from weighted to residue representation
inferred← citeshttps://doi.org/10.1109/12.277299openalex-snapshot
A new class of optimal bounded-degree VLSI sorting networks
inferred← citeshttps://doi.org/10.1109/4.84940openalex-snapshot
Energy consumption in multilective and boundary VLSI computations
inferred← citeshttps://doi.org/10.1109/comhpc.2016.010openalex-snapshot
Network Topologies and Inevitable Contention
inferred← citeshttps://doi.org/10.1109/icassp.1989.266986openalex-snapshot
Parallel processing architectures for iterative image restoration
inferred← citeshttps://doi.org/10.1109/sfcs.1985.39openalex-snapshot
On information flow and sorting : New upper and lower bounds for VLSI circuits
inferred← citeshttps://doi.org/10.1109/spdp.1994.346131openalex-snapshot
Parallelism and locality in priority queues
inferred← citeshttps://doi.org/10.1145/12130.12177openalex-snapshot
Aspects of information flow in VLSI circuits
inferred← citeshttps://doi.org/10.1145/181014.181092openalex-snapshot
AT2 bounds for a class of VLSI problems and string matching
inferred← citeshttps://doi.org/10.1145/210346.210417openalex-snapshot
Deterministic on-line routing on area-universal networks
inferred← citeshttps://doi.org/10.1145/215399.215443openalex-snapshot
Upper bounds to processor-time tradeoffs under bounded-speed message propagation
inferred← citeshttps://doi.org/10.1145/28395.28442openalex-snapshot
Size-time complexity of Boolean networks for prefix computations
inferred← citeshttps://doi.org/10.1145/3181776openalex-snapshot
A Lower Bound Technique for Communication in BSP
inferred← citeshttps://doi.org/10.1145/48014.48017openalex-snapshot
Optimal VLSI circuits for sorting
inferred← citeshttps://doi.org/10.1145/62044.62052openalex-snapshot
Size-time complexity of Boolean networks for prefix computations
inferred← citeshttps://doi.org/10.5555/3018058.3018063openalex-snapshot
Network topologies and inevitable contention
inferred← citeshttps://doi.org/10.62056/avl86cy6bopenalex-snapshot
Lower bounds on the performance of hardware circuits computing the Möbius transform
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.