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Cross-loop reuse analysis and its application to cache optimizations

https://doi.org/10.1007/bfb0017242
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/spe.4380200203openalex-snapshot
Structured dataflow analysis for arrays and its use in an optimizing compiler
inferredcites →https://doi.org/10.1007/3-540-57659-2_13openalex-snapshot
A framework for exploiting data availability to optimize communication
inferredcites →https://doi.org/10.1007/3-540-57659-2_17openalex-snapshot
Program transformation for locality using affinity regions
inferredcites →https://doi.org/10.1007/3-540-57659-2_18openalex-snapshot
Maximizing loop parallelism and improving data locality via loop fusion and distribution
inferredcites →https://doi.org/10.1007/978-1-4684-6894-6openalex-snapshot
Dependence Analysis for Supercomputing
inferredcites →https://doi.org/10.1007/bfb0025884openalex-snapshot
A unified data-flow framework for optimizing communication
inferredcites →https://doi.org/10.1007/bfb0038674openalex-snapshot
On estimating and enhancing cache effectiveness
inferredcites →https://doi.org/10.1016/0743-7315(88)90011-1openalex-snapshot
Analysis of interprocedural side effects in a parallel programming environment
inferredcites →https://doi.org/10.1016/0743-7315(90)90043-oopenalex-snapshot
A mechanism for keeping useful internal information in parallel programming tools: The data access descriptor
inferredcites →https://doi.org/10.1016/s0022-0000(74)80049-8openalex-snapshot
Testing flow graph reducibility
inferredcites →https://doi.org/10.1109/71.86110openalex-snapshot
An implementation of interprocedural bounded regular section analysis
inferredcites →https://doi.org/10.1145/113445.113449openalex-snapshot
A data locality optimizing algorithm
inferredcites →https://doi.org/10.1145/12276.13328openalex-snapshot
Interprocedural dependence analysis and parallelization
inferredcites →https://doi.org/10.1145/143365.143541openalex-snapshot
Access normalization
inferredcites →https://doi.org/10.1145/178243.178253openalex-snapshot
GIVE-N-TAKE—a balanced code placement framework
inferredcites →https://doi.org/10.1145/183018.183032openalex-snapshot
Shade: a fast instruction-set simulator for execution profiling
inferredcites →https://doi.org/10.1145/195473.195557openalex-snapshot
Compiler optimizations for improving data locality
inferredcites →https://doi.org/10.1145/2591635.2667157openalex-snapshot
Analysis of interprocedural side effects in a parallel programming environment
inferredcites →https://doi.org/10.1145/3392717.3400034openalex-snapshot
Optimizing supercompilers for supercomputers
inferredcites →https://doi.org/10.1145/93542.93553openalex-snapshot
Improving register allocation for subscripted variables
inferredcites →https://doi.org/10.1145/989393.989411openalex-snapshot
Interprocedural dependence analysis and parallelization
inferredcites →https://doi.org/10.1145/989393.989428openalex-snapshot
Improving register allocation for subscripted variables

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1006/jpdc.1997.1310openalex-snapshot
Communication-Minimal Tiling of Uniform Dependence Loops
inferred← citeshttps://doi.org/10.1007/bfb0017262openalex-snapshot
Communication-minimal tiling of uniform dependence loops
inferred← citeshttps://doi.org/10.1007/bfb0032681openalex-snapshot
Reuse-driven tiling for data locality
inferred← citeshttps://doi.org/10.1109/sisw.2007.11openalex-snapshot
G_{its}^2 VSR: An Information Theoretical Secure Verifiable Secret Redistribution Protocol for Long-term Archival Storage
inferred← citeshttps://doi.org/10.1109/sisw.2007.8openalex-snapshot
Securing Disk-Resident Data through Application Level Encryption
inferred← citeshttps://doi.org/10.1145/1113830.1113835openalex-snapshot
Compiler-directed high-level energy estimation and optimization
inferred← citeshttps://doi.org/10.1145/1133255.1134004openalex-snapshot
Reducing NoC energy consumption through compiler-directed channel voltage scaling
inferred← citeshttps://doi.org/10.1145/237090.237161openalex-snapshot
A quantitative analysis of loop nest locality
inferred← citeshttps://doi.org/10.1145/248208.237161openalex-snapshot
A quantitative analysis of loop nest locality
inferred← citeshttps://doi.org/10.1145/248209.237161openalex-snapshot
A quantitative analysis of loop nest locality
inferred← citeshttps://doi.org/10.1145/291069.291010openalex-snapshot
Compiler-controlled memory
inferred← citeshttps://doi.org/10.1145/329466.329484openalex-snapshot
Quantifying loop nest locality using SPEC'95 and the perfect benchmarks
inferred← citeshttps://doi.org/10.1145/951710.951714openalex-snapshot
Vectorizing for a SIMdD DSP architecture
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