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On estimating and enhancing cache effectiveness

https://doi.org/10.1007/bfb0038674
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-18991-2_14openalex-snapshot
Strategies for cache and local memory management by global program transformation
inferredcites →https://doi.org/10.1007/978-1-4684-6894-6openalex-snapshot
Dependence Analysis for Supercomputing
inferredcites →https://doi.org/10.1016/0743-7315(88)90015-9openalex-snapshot
An overview of the PTRAN analysis system for multiprocessing
inferredcites →https://doi.org/10.1016/0743-7315(90)90043-oopenalex-snapshot
A mechanism for keeping useful internal information in parallel programming tools: The data access descriptor
inferredcites →https://doi.org/10.1109/superc.1990.130070openalex-snapshot
Data cache performance of supercomputer applications
inferredcites →https://doi.org/10.1145/106972.106981openalex-snapshot
The cache performance and optimizations of blocked algorithms
inferredcites →https://doi.org/10.1145/12276.13328openalex-snapshot
Interprocedural dependence analysis and parallelization
inferredcites →https://doi.org/10.1145/2591635.2667155openalex-snapshot
Strategies for cache and local memory management by global program transformation
inferredcites →https://doi.org/10.1145/2591635.2667156openalex-snapshot
An overview of the PTRAN analysis system for multiprocessing
inferredcites →https://doi.org/10.1145/3392717.3400034openalex-snapshot
Optimizing supercompilers for supercomputers
inferredcites →https://doi.org/10.1145/55364.55388openalex-snapshot
On the problem of optimizing data transfers for complex memory systems
inferredcites →https://doi.org/10.1145/73141.74845openalex-snapshot
Determining average program execution times and their variance
inferredcites →https://doi.org/10.1145/7902.7904openalex-snapshot
Advanced compiler optimizations for supercomputers
inferredcites →https://doi.org/10.1145/989393.989411openalex-snapshot
Interprocedural dependence analysis and parallelization
inferredcites →https://doi.org/10.1147/rd.341.0012openalex-snapshot
The IBM RISC System/6000 processor: Hardware overview
inferredcites →https://doi.org/10.5555/110382.110587openalex-snapshot
Data cache performance of supercomputer applications

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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A Framework for Qualitative Performance Prediction
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