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A Petri Net approach for the analysis of VHDL descriptions

https://doi.org/10.1007/bfb0021711
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-12275-3openalex-snapshot
CONLAN Report
inferredcites →https://doi.org/10.1109/2.65openalex-snapshot
Formal verification of hardware correctness: introduction and survey of current research
inferredcites →https://doi.org/10.1109/5.24143openalex-snapshot
Petri nets: Properties, analysis and applications
inferredcites →https://doi.org/10.1145/42192.45067openalex-snapshot
Systems semantics: principles, applications, and implementation
inferredcites →https://doi.org/10.1145/800055.802026openalex-snapshot
muFP, a language for VLSI design

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/0-387-28327-7_5openalex-snapshot
Verification of Control Paths Using Petri Nets
inferred← citeshttps://doi.org/10.1007/3-540-60385-9_18openalex-snapshot
Semantics of a verification-oriented subset of VHDL
inferred← citeshttps://doi.org/10.1007/3-540-60385-9_20openalex-snapshot
A symbolic relation for a subset of VHDL'87 descriptions and its application to symbolic model checking
inferred← citeshttps://doi.org/10.1007/3-540-61648-9_59openalex-snapshot
A tool for translation of VHDL descriptions into a formal model and its application to formal verification and synthesis
inferred← citeshttps://doi.org/10.1007/978-3-642-60641-0_11openalex-snapshot
VHDL Formal Modeling and Analysis
inferred← citeshttps://doi.org/10.1007/bf01383875openalex-snapshot
A Colored Petri Net model of VHDL
inferred← citeshttps://doi.org/10.1109/66.705370openalex-snapshot
Modeling, analysis, simulation, scheduling, and control of semiconductor manufacturing systems: A Petri net approach
inferred← citeshttps://doi.org/10.1109/eurdac.1993.410687openalex-snapshot
Toward a formal semantics of IEEE Std. VHDL 1076
inferred← citeshttps://doi.org/10.1109/eurmic.1998.711818openalex-snapshot
Formal extraction of memorizing elements for sequential VHDL synthesis
inferred← citeshttps://doi.org/10.1109/icsmc.2001.972973openalex-snapshot
Verification of digital control paths using Petri nets
inferred← citeshttps://doi.org/10.1109/icvd.1999.745140openalex-snapshot
Formal analysis of single WAIT VHDL processes for semantic based synthesis
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