On the public citation graph
Formal verification of digital circuits using symbolic ternary system models
0 signed · 76 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1049/ip-i-1.1981.0010openalex-snapshot
Introduction to V.L.S.I. Systems
inferredcites →https://doi.org/10.1109/43.62795openalex-snapshot
Formal verification of memory circuits by switch-level simulation
inferredcites →https://doi.org/10.1109/iccd.1989.63359openalex-snapshot
Verifying pipelined hardware using symbolic logic simulation
inferredcites →https://doi.org/10.1109/tc.1979.1675317openalex-snapshot
On a Ternary Model of Gate Networks
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1109/tcad.1987.1270310openalex-snapshot
Boolean Analysis of MOS Circuits
inferredcites →https://doi.org/10.1109/tcad.1987.1270320openalex-snapshot
Fast Methods for Switch-Level Verification of MOS Circuits
inferredcites →https://doi.org/10.1145/123186.123223openalex-snapshot
Sequential circuit verification using symbolic model checking
inferredcites →https://doi.org/10.1145/37888.37890openalex-snapshot
COSMOS: a compiled simulator for MOS circuits
inferredcites →https://doi.org/10.1145/37888.37929openalex-snapshot
On the verification of sequential machines at differing levels of abstraction
inferredcites →https://doi.org/10.1145/5397.5399openalex-snapshot
Automatic verification of finite-state concurrent systems using temporal logic specifications
inferredcites →https://doi.org/10.5555/800292.811742openalex-snapshot
The application of program verification techniques to hardware verification
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11691372_9openalex-snapshot
SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver
inferred← citeshttps://doi.org/10.1007/3-540-36126-x_5openalex-snapshot
Generalized Symbolic Trajectory Evaluation — Abstraction in Action
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_17openalex-snapshot
Verification of Infinite State Systems by Compositional Model Checking
inferred← citeshttps://doi.org/10.1007/3-540-55179-4_29openalex-snapshot
A two-level formal verification methodology using HOL and COSMOS
inferred← citeshttps://doi.org/10.1007/3-540-56944-8_50openalex-snapshot
Verification of Switch-level designs with many-valued logic
inferred← citeshttps://doi.org/10.1007/3-540-58043-3_19openalex-snapshot
Verification tools for finite-state concurrent systems
inferred← citeshttps://doi.org/10.1007/3-540-63166-6_25openalex-snapshot
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
inferred← citeshttps://doi.org/10.1007/3-540-63475-4_1openalex-snapshot
Symbolic trajectory evaluation
inferred← citeshttps://doi.org/10.1007/978-1-4615-3556-0_2openalex-snapshot
Formal Hardware Verification Methods: A Survey
inferred← citeshttps://doi.org/10.1007/978-3-032-15700-3_12openalex-snapshot
Input-Based Three-Valued Abstraction Refinement
inferred← citeshttps://doi.org/10.1007/978-3-319-21668-3_8openalex-snapshot
Word-Level Symbolic Trajectory Evaluation
inferred← citeshttps://doi.org/10.1007/978-3-319-98047-8_16openalex-snapshot
Are Synchronous Programs Logic Programs?
inferred← citeshttps://doi.org/10.1007/978-3-540-69850-0_8openalex-snapshot
Fifteen Years of Formal Property Verification in Intel
inferred← citeshttps://doi.org/10.1007/978-3-642-33386-6_1openalex-snapshot
Verification of Computer Switching Networks: An Overview
inferred← citeshttps://doi.org/10.1007/978-94-017-0452-6_5openalex-snapshot
Advanced Many-Valued Logics
inferred← citeshttps://doi.org/10.1007/978-94-017-1754-0_9openalex-snapshot
Tableaux for Many-Valued Logics
inferred← citeshttps://doi.org/10.1007/bf00121125openalex-snapshot
Formal hardware verification methods: A survey
inferred← citeshttps://doi.org/10.1007/bf01383966openalex-snapshot
Formal verification by symbolic evaluation of partially-ordered trajectories
inferred← citeshttps://doi.org/10.1007/s10703-005-2250-1openalex-snapshot
A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor
inferred← citeshttps://doi.org/10.1007/s10703-017-0268-9openalex-snapshot
Symbolic trajectory evaluation for word-level verification: theory and implementation
inferred← citeshttps://doi.org/10.1016/b978-0-444-89880-7.50037-1openalex-snapshot
Operational Semantics Based Formal Symbolic Simulation
inferred← citeshttps://doi.org/10.1016/b978-012443880-4/50059-4openalex-snapshot
Microprocessor Systems
inferred← citeshttps://doi.org/10.1016/b978-044450813-3/50022-9openalex-snapshot
Automated Deduction for Many-Valued Logics
inferred← citeshttps://doi.org/10.1016/s1571-0661(04)80410-9openalex-snapshot
Liveness Checking as Safety Checking
inferred← citeshttps://doi.org/10.1023/a:1022917321255openalex-snapshot
Formal Verification Successes at Motorola
inferred← citeshttps://doi.org/10.1093/oso/9780198539896.001.0001openalex-snapshot
Automated Deduction in Multiple-valued Logics
inferred← citeshttps://doi.org/10.1109/43.275352openalex-snapshot
Symbolic model checking for sequential circuit verification
inferred← citeshttps://doi.org/10.1109/43.771176openalex-snapshot
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
inferred← citeshttps://doi.org/10.1109/54.895007openalex-snapshot
Validating PowerPC microprocessor custom memories
inferred← citeshttps://doi.org/10.1109/54.936246openalex-snapshot
Design and development paradigm for industrial formal verification CAD tools
inferred← citeshttps://doi.org/10.1109/7384.982895openalex-snapshot
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation: a summary
inferred← citeshttps://doi.org/10.1109/acsd.2008.4574599openalex-snapshot
Performing causality analysis by bounded model checking
inferred← citeshttps://doi.org/10.1109/asic.2002.1158031openalex-snapshot
Using formal techniques for identifying uninitialized registers in SoC designs
inferred← citeshttps://doi.org/10.1109/comst.2014.2345792openalex-snapshot
Applying Formal Methods to Networking: Theory, Techniques, and Applications
inferred← citeshttps://doi.org/10.1109/hicss.1995.375412openalex-snapshot
Symbolic incompletely specified functions for correct evaluation in the presence of indeterminate input values
inferred← citeshttps://doi.org/10.1109/iccad.2002.1167584openalex-snapshot
GSTE through a case study [digital IC verification]
inferred← citeshttps://doi.org/10.1109/iccd.1995.528929openalex-snapshot
Extraction of finite state machines from transistor netlists by symbolic simulation
inferred← citeshttps://doi.org/10.1109/icvd.2004.1260913openalex-snapshot
Towards the complete elimination of gate/switch level simulations
inferred← citeshttps://doi.org/10.1109/ismvl.1994.302226openalex-snapshot
Digital circuit verification using partially-ordered state models
inferred← citeshttps://doi.org/10.1109/ismvl.2007.57openalex-snapshot
Towards First-Order Symbolic Trajectory Evaluation
inferred← citeshttps://doi.org/10.1109/ismvl64713.2025.00039openalex-snapshot
Normal Forms and Decompositions of Monotone Ternary Functions
inferred← citeshttps://doi.org/10.1109/isqed.2001.915203openalex-snapshot
Concrete impact of formal verification on quality in IP design and implementation
inferred← citeshttps://doi.org/10.1109/mtv.2007.13openalex-snapshot
A Scalable Symbolic Simulator for Verilog RTL
inferred← citeshttps://doi.org/10.1109/tcad.2013.2292501openalex-snapshot
Latency Analysis for Sequential Circuits
inferred← citeshttps://doi.org/10.1109/test.1996.557147openalex-snapshot
PowerPC/sup (TM)/ array verification methodology using formal techniques
inferred← citeshttps://doi.org/10.1109/test.2002.1041762openalex-snapshot
Combining ATPG and symbolic simulation for efficient validation of embedded array systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2003.812320openalex-snapshot
Introduction to generalized symbolic trajectory evaluation
inferred← citeshttps://doi.org/10.1109/vtest.2000.843820openalex-snapshot
Validation of PowerPC/sup TM/ custom memories using symbolic simulation
inferred← citeshttps://doi.org/10.1109/vts.2002.1011152openalex-snapshot
Is state mapping essential for equivalence checking custom memories in scan-based designs?
inferred← citeshttps://doi.org/10.1145/127601.127701openalex-snapshot
Formal hardware verification by symbolic ternary trajectory evaluation
inferred← citeshttps://doi.org/10.1145/127601.127702openalex-snapshot
Representing circuits more efficiently in symbolic model checking
inferred← citeshttps://doi.org/10.1145/157485.164981openalex-snapshot
Linking BDD-based symbolic evaluation to interactive theorem-proving
inferred← citeshttps://doi.org/10.1145/774572.774573openalex-snapshot
Comprehensive frequency-dependent substrate noise analysis using boundary element methods
inferred← citeshttps://doi.org/10.14288/1.0051407openalex-snapshot
Compositional model checking of partially ordered state spaces
inferred← citeshttps://doi.org/10.1504/ijes.2005.008805openalex-snapshot
A methodology for validation of microprocessors using symbolic simulation
inferred← citeshttps://doi.org/10.18255/1818-1015-2019-3-332-350openalex-snapshot
Formal Verification of Three-Valued Digital Waveforms
inferred← citeshttps://doi.org/10.21236/ada256078openalex-snapshot
Representation and Manipulation of Inductive Boolean Functions
inferred← citeshttps://doi.org/10.3103/s0146411620070135openalex-snapshot
Formal Verification of Three-Valued Digital Waveforms
inferred← citeshttps://doi.org/10.48550/arxiv.1505.07916openalex-snapshot
Word-level Symbolic Trajectory Evaluation
inferred← citeshttps://doi.org/10.70675/38dcf47bz60b4z4a7dzb09fz43d98be9b60fopenalex-snapshot
Effective Encoding of Critical Systems for SAT-Based Model Checking.
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.