On the public citation graph

Using partial-order semantics to avoid the state explosion problem in asynchronous systems

https://doi.org/10.1007/bfb0023728
0 signed · 40 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf01379149openalex-snapshot
Modeling concurrency with partial orders
inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot
Compiling communicating processes into delay-insensitive VLSI circuits
inferredcites →https://doi.org/10.1007/bfb0031414openalex-snapshot
Trace Theory and VLSJ Design
inferredcites →https://doi.org/10.1109/12.2209openalex-snapshot
Abstract specification of synchronous data types for VLSI and proving the correctness of systolic network implementations
inferredcites →https://doi.org/10.1145/41625.41626openalex-snapshot
Specification and verification of concurrent programs by A ∀ automata
inferredcites →https://doi.org/10.7551/mitpress/6874.001.0001openalex-snapshot
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/0471224146.biblioopenalex-snapshot
References
inferred← citeshttps://doi.org/10.1006/inco.1994.1035openalex-snapshot
A Partial Approach to Model Checking
inferred← citeshttps://doi.org/10.1007/3-540-55179-4_31openalex-snapshot
Partial-order model checking: A guide for the perplexed
inferred← citeshttps://doi.org/10.1007/3-540-55179-4_32openalex-snapshot
Using partial orders for the efficient verification of deadlock freedom and safety properties
inferred← citeshttps://doi.org/10.1007/3-540-56496-9_11openalex-snapshot
Verifying timed behavior automata with nonbinary delay constraints
inferred← citeshttps://doi.org/10.1007/3-540-56496-9_14openalex-snapshot
Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits
inferred← citeshttps://doi.org/10.1007/3-540-56922-7_35openalex-snapshot
Verifying timed behavior automata with input/output critical races
inferred← citeshttps://doi.org/10.1007/3-540-56922-7_36openalex-snapshot
Refining dependencies improves partial-order verification methods (extended abstract)
inferred← citeshttps://doi.org/10.1007/3-540-56922-7_39openalex-snapshot
Generation of reduced models for checking fragments of CTL
inferred← citeshttps://doi.org/10.1007/3-540-57208-2_17openalex-snapshot
Partial-order methods for temporal verification
inferred← citeshttps://doi.org/10.1007/3-540-58043-3_19openalex-snapshot
Verification tools for finite-state concurrent systems
inferred← citeshttps://doi.org/10.1007/3-540-60045-0_50openalex-snapshot
Trace theoretic verification of asynchronous circuits using unfoldings
inferred← citeshttps://doi.org/10.1007/978-0-387-35062-2_11openalex-snapshot
An approach for testing asynchronous communicating systems
inferred← citeshttps://doi.org/10.1007/978-0-387-35578-8_19openalex-snapshot
An enhanced model for testing asynchronous communicating systems
inferred← citeshttps://doi.org/10.1007/978-1-4471-3860-0_20openalex-snapshot
Modelling Reactive Hardware Processes Using Partial Orders
inferred← citeshttps://doi.org/10.1007/bf00121261openalex-snapshot
Automatic verification of distributed systems: The process algebra approach
inferred← citeshttps://doi.org/10.1007/bf00464356openalex-snapshot
Specification and automatic verification of self-timed queues
inferred← citeshttps://doi.org/10.1007/bf01383879openalex-snapshot
Using partial orders for the efficient verification of deadlock freedom and safety properties
inferred← citeshttps://doi.org/10.1007/bf01384314openalex-snapshot
A technique of state space search based on unfolding
inferred← citeshttps://doi.org/10.1007/bf01384316openalex-snapshot
Using integer programming to verify general safety and liveness properties
inferred← citeshttps://doi.org/10.1016/0890-5401(92)90017-aopenalex-snapshot
Symbolic model checking: 1020 States and beyond
inferred← citeshttps://doi.org/10.1023/a:1022902408130openalex-snapshot
True Concurrency in Models of Asynchronous Circuit Behavior
inferred← citeshttps://doi.org/10.1109/12.368014openalex-snapshot
An automaton model for scheduling constraints in synchronous machines
inferred← citeshttps://doi.org/10.1109/52.108773openalex-snapshot
Protocol design: redefining the state of the art
inferred← citeshttps://doi.org/10.1109/apsec.2007.32openalex-snapshot
Checking Distributed Programs with Partially Ordered Atoms
inferred← citeshttps://doi.org/10.1109/aspec.2007.39openalex-snapshot
Checking Distributed Programs with Partially Ordered Atoms
inferred← citeshttps://doi.org/10.1109/icccn.2000.885549openalex-snapshot
Systematic testing of multicast routing protocols: analysis of forward and backward search techniques
inferred← citeshttps://doi.org/10.1109/wcadm.1995.514650openalex-snapshot
Hierarchical gate-level verification of speed-independent circuits
inferred← citeshttps://doi.org/10.1137/0406035openalex-snapshot
Complexity Results for POMSET Languages
inferred← citeshttps://doi.org/10.1145/2043643.2043650openalex-snapshot
Relativistic Causality and Clockless Circuits
inferred← citeshttps://doi.org/10.3390/math11010047openalex-snapshot
The Unfolding: Origins, Techniques, and Applications within Discrete Event Systems
inferred← citeshttps://doi.org/10.5555/113938.149395openalex-snapshot
The Princeton University behavioral synthesis system
inferred← citeshttps://doi.org/10.5555/159754.161737openalex-snapshot
Verification of digital circuits based on formal semantics of a hardware description language
inferred← citeshttps://doi.org/10.6100/ir462072openalex-snapshot
Abstract interpretation and partition refinement for model checking
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.