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Specification and automatic verification of self-timed queues
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-52148-8_17openalex-snapshot
Timing assumptions and verification of finite-state concurrent systems
inferredcites →https://doi.org/10.1007/3-540-52148-8_28openalex-snapshot
Combining CTL, trace theory and timing models
inferredcites →https://doi.org/10.1007/3-540-52148-8_30openalex-snapshot
Verification of synchronous sequential machines based on symbolic execution
inferredcites →https://doi.org/10.1007/3-540-52559-9_74openalex-snapshot
Analysis of discrete event coordination
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_3openalex-snapshot
HOL: A Proof Generating System for Higher-Order Logic
inferredcites →https://doi.org/10.1007/978-3-642-95432-0_13openalex-snapshot
Trace Theory and the Definition of Hierarchical Components
inferredcites →https://doi.org/10.1007/bf00709154openalex-snapshot
A stubborn attack on state explosion
inferredcites →https://doi.org/10.1007/bf01660032openalex-snapshot
A formal model for defining and classifying delay-insensitive circuits and systems
inferredcites →https://doi.org/10.1007/bfb0023728openalex-snapshot
Using partial-order semantics to avoid the state explosion problem in asynchronous systems
inferredcites →https://doi.org/10.1007/bfb0032042openalex-snapshot
Automata for modeling real-time systems
inferredcites →https://doi.org/10.1016/0010-4485(86)90136-3openalex-snapshot
1985 Chapel Hill Conference on very large scale integration
inferredcites →https://doi.org/10.1016/0096-0551(80)90011-9openalex-snapshot
Introduction to automata theory, languages, and computation
inferredcites →https://doi.org/10.1016/0378-4754(81)90068-9openalex-snapshot
Introduction to automata theory, languages and computation
inferredcites →https://doi.org/10.1016/0378-4754(82)90066-0openalex-snapshot
Petri Net theory and the modeling of systems
inferredcites →https://doi.org/10.1016/0890-5401(92)90017-aopenalex-snapshot
Symbolic model checking: 1020 States and beyond
inferredcites →https://doi.org/10.1016/s0167-9260(86)80002-5openalex-snapshot
On the models for designing VLSI asynchronous digital systems
inferredcites →https://doi.org/10.1049/ip-e:19860034openalex-snapshot
Automatic verification of asynchronous circuits using temporal logic
inferredcites →https://doi.org/10.1108/ir.1999.04926fae.001openalex-snapshot
Lecture Notes in Computer Science 1205
inferredcites →https://doi.org/10.1109/43.177405openalex-snapshot
Optimized synthesis of asynchronous control circuits from graph-theoretic specifications
inferredcites →https://doi.org/10.1109/43.41504openalex-snapshot
Automatic synthesis of asynchronous circuits from high-level specifications
inferredcites →https://doi.org/10.1109/iccad.1990.129875openalex-snapshot
Optimized synthesis of asynchronous control circuits from graph-theoretic specifications
inferredcites →https://doi.org/10.1109/lics.1990.113763openalex-snapshot
A logic of concrete time intervals
inferredcites →https://doi.org/10.1109/lics.1990.113766openalex-snapshot
Model-checking for real-time systems
inferredcites →https://doi.org/10.1145/127601.127685openalex-snapshot
Algorithms for synthesis of hazard-free asynchronous circuits
inferredcites →https://doi.org/10.6100/ir25052openalex-snapshot
Classification and composition of delay-insensitive circuits
inferredcites →https://doi.org/10.7551/mitpress/6874.001.0001openalex-snapshot
Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-49253-4_7openalex-snapshot
Verification of Bounded Delay Asynchronous Circuits with Timed Traces
inferred← citeshttps://doi.org/10.1007/978-1-4471-3575-3_1openalex-snapshot
Asynchronous Circuit Design: Motivation, Background, & Methods
inferred← citeshttps://doi.org/10.1007/bf00935211openalex-snapshot
Bubbles can make self-timed pipelines fast
inferred← citeshttps://doi.org/10.1016/0167-6423(96)00005-6openalex-snapshot
Design and analysis of up-down counters
inferred← citeshttps://doi.org/10.1109/32.295890openalex-snapshot
Specification and validation of control-intensive IC's in hopCP
inferred← citeshttps://doi.org/10.1109/3477.865185openalex-snapshot
Correctness in hierarchical knowledge-based requirements
inferred← citeshttps://doi.org/10.1109/43.329261openalex-snapshot
A correctness criterion for asynchronous circuit validation and optimization
inferred← citeshttps://doi.org/10.1109/92.748198openalex-snapshot
Peephole optimization of asynchronous macromodule networks
inferred← citeshttps://doi.org/10.1109/async.1994.656309openalex-snapshot
A technique for estimating power in asynchronous circuits
inferred← citeshttps://doi.org/10.1109/async.1996.494443openalex-snapshot
On the correctness of the Sproull counterflow pipeline processor
inferred← citeshttps://doi.org/10.1109/async.1996.494447openalex-snapshot
Using partial orders for trace theoretic verification of asynchronous circuits
inferred← citeshttps://doi.org/10.1109/async.2000.837024openalex-snapshot
Low-latency asynchronous FIFO's using token rings
inferred← citeshttps://doi.org/10.1109/ccece.1993.332461openalex-snapshot
Testing the consequences of specifications in modal μ
inferred← citeshttps://doi.org/10.1109/date.2002.998294openalex-snapshot
A burst-mode oriented back-end for the Balsa synthesis system
inferred← citeshttps://doi.org/10.1109/edtc.1994.326848openalex-snapshot
A generalized signal transition graph model for specification of complex interfaces
inferred← citeshttps://doi.org/10.1109/iccd.1994.331892openalex-snapshot
Performance analysis and optimization of asynchronous circuits
inferred← citeshttps://doi.org/10.1109/iccd.1994.331946openalex-snapshot
Peephole optimization of asynchronous macromodule networks
inferred← citeshttps://doi.org/10.1109/iccd.2003.1240869openalex-snapshot
Verification of timed circuits with failure directed abstractions
inferred← citeshttps://doi.org/10.1109/tcad.2003.816214openalex-snapshot
Modular verification of timed circuits using automatic abstraction
inferred← citeshttps://doi.org/10.1109/tcad.2005.854638openalex-snapshot
Verification of timed circuits with failure-directed abstractions
inferred← citeshttps://doi.org/10.1109/tencon.2004.1414526openalex-snapshot
Inductive temporal formula specifications
inferred← citeshttps://doi.org/10.1109/tencon.2005.301198openalex-snapshot
An Efficient Temporal Formula Specification Method for Asynchronous Concurrent Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2004.831476openalex-snapshot
Robust interfaces for mixed-timing systems
inferred← citeshttps://doi.org/10.5555/882452.874506openalex-snapshot
A Burst-Mode Oriented Back-End for the Balsa Synthesis System
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