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Slack elasticity in concurrent computing

https://doi.org/10.1007/bfb0054295
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf00261260openalex-snapshot
An axiomatic definition of synchronization primitives
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Trace Theory and VLSJ Design
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The probe: An addition to communication primitives
inferredcites →https://doi.org/10.1109/arvlsi.1997.634853openalex-snapshot
The design of an asynchronous MIPS R3000 microprocessor
inferredcites →https://doi.org/10.1145/357980.358021openalex-snapshot
Communicating sequential processes
inferredcites →https://doi.org/10.1145/359576.359585openalex-snapshot
Communicating sequential processes
inferredcites →https://doi.org/10.7907/exek9-qb507openalex-snapshot
An Approach to Concurrent Semantics Using Complete Traces
inferredcites →https://doi.org/10.7907/kgstw-em803openalex-snapshot
The impact of asynchrony on computer architecture

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Floating Time Transition System: More Efficient Analysis of Timed Actors
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Programmable Asynchronous Pipeline Arrays
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Elasticity and Petri Nets
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Reduced Execution Semantics of MPI: From Theory to Practice
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Precise Dynamic Analysis for Slack Elasticity: Adding Buffering without Adding Bugs
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Challenges in Verifying Communication Fabrics
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Pipeline performance
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Time elastic digital systems and Petri Nets
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Energy-efficient pipelines
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Static tokens: using data .ow to automate concurrent pipeline synthesis
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Slack Matching Asynchronous Designs
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Slack Matching Quasi Delay-Insensitive Circuits
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Design of a High-Speed Asynchronous Turbo Decoder
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Concurrency-Enhancing Transformations for Asynchronous Behavioral Specifications: A Data-Driven Approach
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Automatic Clock: A Promising Approach toward GALSification
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Elastic Bundles: Modelling and Synthesis of Asynchronous Circuits with Granular Rigidity
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Scaledmatx One : A Bundled-Data GALS Inference ASIC
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Translating General Slack Elastic Programs into Dataflow Circuits
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Automated Decomposition of Concurrent Programs for Asynchronous Logic Synthesis
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Description-Level Optimisation of Synthesisable Asynchronous Circuits
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Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA
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Fault detection and isolation techniques for quasi delay-insensitive circuits
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Synchronous Elastic Networks
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Removing concurrency for rapid functional verification
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Data-driven process decomposition for circuit synthesis
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Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading
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RTL Synthesis: From Logic Synthesis to Automatic Pipelining
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Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
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Synthesis and Optimization of Pipelined Packet Processors
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Elastic Circuits
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Buffer Placement and Sizing for High-Performance Dataflow Circuits
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Throughput Optimization of Quasi Delay Insensitive Circuits via Slack Matching
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