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Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/0-306-47003-9_24openalex-snapshot
SVL: A Scripting Language for Compositional Verification
inferredcites →https://doi.org/10.1007/0-387-33403-3_6openalex-snapshot
Validation of Asynchronous Circuit Specifications Using IF/CADP
inferredcites →https://doi.org/10.1007/11589976_17openalex-snapshot
Translating Hardware Process Algebras into Standard Process Algebras: Illustration with CHP and LOTOS
inferredcites →https://doi.org/10.1007/3-540-45937-5_3openalex-snapshot
Compiler Construction Using LOTOS NT
inferredcites →https://doi.org/10.1007/978-0-387-35533-7_17openalex-snapshot
Verifying and Testing Asynchronous Circuits Using Lotos
inferredcites →https://doi.org/10.1007/978-1-4419-5906-5_568openalex-snapshot
Data Encryption Standard (DES)
inferredcites →https://doi.org/10.1007/bf01660032openalex-snapshot
A formal model for defining and classifying delay-insensitive circuits and systems
inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot
Compiling communicating processes into delay-insensitive VLSI circuits
inferredcites →https://doi.org/10.1007/bfb0054295openalex-snapshot
Slack elasticity in concurrent computing
inferredcites →https://doi.org/10.1016/0020-0190(85)90078-xopenalex-snapshot
The probe: An addition to communication primitives
inferredcites →https://doi.org/10.1016/0141-9331(86)90196-1openalex-snapshot
Communicating sequential processes
inferredcites →https://doi.org/10.1016/0167-6423(90)90076-popenalex-snapshot
Communication and concurrency
inferredcites →https://doi.org/10.1016/0169-7552(87)90085-7openalex-snapshot
Introduction to the ISO specification language LOTOS
inferredcites →https://doi.org/10.1016/j.ipl.2003.12.007openalex-snapshot
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench
inferredcites →https://doi.org/10.1016/s0167-6423(02)00094-1openalex-snapshot
Efficient on-the-fly model-checking for regular alternation-free mu-calculus
inferredcites →https://doi.org/10.1093/comjnl/45.1.12openalex-snapshot
Balsa: An Asynchronous Hardware Synthesis Language
inferredcites →https://doi.org/10.1109/71.877831openalex-snapshot
The odd-even turn model for adaptive routing
inferredcites →https://doi.org/10.1109/acsd.2006.16openalex-snapshot
On process-algebraic verification of asynchronous circuits
inferredcites →https://doi.org/10.1109/async.2005.10openalex-snapshot
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
inferredcites →https://doi.org/10.1109/async.2006.16openalex-snapshot
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
inferredcites →https://doi.org/10.1109/iccad.1989.76950openalex-snapshot
Practicality of state-machine verification of speed-independent circuits
inferredcites →https://doi.org/10.1109/memcod.2009.5185377openalex-snapshot
Verification of an industrial SystemC/TLM model using LOTOS and CADP
inferredcites →https://doi.org/10.1145/370155.370339openalex-snapshot
The tangram framework (embedded tutorial)
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.2139/ssrn.4819131openalex-extracted
The Beauty and the Beast: Sok on Process Algebras and Cybersecurity
inferred← citeshttps://doi.org/10.1007/978-3-030-00244-2_13openalex-snapshot
Compositional Verification in Action
inferred← citeshttps://doi.org/10.1007/978-3-319-10702-8_4openalex-snapshot
Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip
inferred← citeshttps://doi.org/10.1007/978-3-540-68237-0_12openalex-snapshot
A Model Checking Language for Concurrent Value-Passing Systems
inferred← citeshttps://doi.org/10.1007/s00165-009-0133-8openalex-snapshot
Translating FSP into LOTOS and networks of automata
inferred← citeshttps://doi.org/10.1016/j.entcs.2008.04.009openalex-snapshot
Reflections on the Future of Concurrency Theory in General and Process Calculi in Particular
inferred← citeshttps://doi.org/10.1016/j.entcs.2009.07.025openalex-snapshot
Modeling and Analyzing the Implementation of Latency-Insensitive Protocols Using the Polychrony Framework
inferred← citeshttps://doi.org/10.1016/j.ins.2007.10.023openalex-snapshot
ACTLW – An action-based computation tree logic with unless operator
inferred← citeshttps://doi.org/10.1016/j.scico.2008.09.011openalex-snapshot
On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP
inferred← citeshttps://doi.org/10.1016/j.scico.2016.01.002openalex-snapshot
An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis
inferred← citeshttps://doi.org/10.1109/async.2018.00021openalex-snapshot
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits
inferred← citeshttps://doi.org/10.1109/date.2008.4484666openalex-snapshot
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures
inferred← citeshttps://doi.org/10.1109/icgcs.2010.5543050openalex-snapshot
Formal modeling and verification for Network-on-chip
inferred← citeshttps://doi.org/10.1109/issoc.2014.6972449openalex-snapshot
Formal verification of circuit-switched Network on chip (NoC) architectures using SPIN
inferred← citeshttps://doi.org/10.1109/isvlsi.2011.57openalex-snapshot
Application of Formal Methods for System-Level Verification of Network on Chip
inferred← citeshttps://doi.org/10.1109/isvlsi.2012.31openalex-snapshot
Formal Estimation of Worst-Case Communication Latency in a Network-on-Chip
inferred← citeshttps://doi.org/10.1109/nesea.2011.6144950openalex-snapshot
CorreComm: A formal hierarchical framework for communication designs
inferred← citeshttps://doi.org/10.1109/nocs.2012.26openalex-snapshot
A Mixed Verification Strategy Tailored for Networks on Chip
inferred← citeshttps://doi.org/10.1109/snpd.2012.88openalex-snapshot
An Approach to Modeling and Verifying Router-Based Network
inferred← citeshttps://doi.org/10.1109/tcad.2008.2010691openalex-snapshot
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
inferred← citeshttps://doi.org/10.1145/1403375.1403399openalex-snapshot
Quantitative evaluation in embedded system design
inferred← citeshttps://doi.org/10.1155/2009/548324openalex-snapshot
A Formal Approach to the Verification of Networks on Chip
inferred← citeshttps://doi.org/10.1561/1000000011openalex-snapshot
The Chip Is the Network: Toward a Science of Network-on-Chip Design
inferred← citeshttps://doi.org/10.1561/1500000011openalex-snapshot
Opinion Mining and Sentiment Analysis
inferred← citeshttps://doi.org/10.5555/3108905.3108914openalex-snapshot
Modeling and verification of network-on-chip using constrained-DEVS
inferred← citeshttps://doi.org/10.70675/f79a290azc193z4d7fza536zffe11157794bopenalex-snapshot
Méthodes Formelles pour la vérification fonctionnelle des systèmes sur puce cache cohérent
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