On the public citation graph
On the effectiveness of theorem proving guided discovery of formal assertions for a register allocator in a high-level synthesis system
0 signed · 26 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-55602-8_217openalex-snapshot
PVS: A prototype verification system
inferredcites →https://doi.org/10.1007/3-540-58450-1_50openalex-snapshot
An engineering approach to formal digital system design
inferredcites →https://doi.org/10.1007/978-1-4613-1519-3openalex-snapshot
Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench
inferredcites →https://doi.org/10.1007/bfb0105403openalex-snapshot
Implementation issues about the embedding of existing high level synthesis algorithms in HOL
inferredcites →https://doi.org/10.1016/s0167-5060(04)x8001-8openalex-snapshot
Algorithmic Graph Theory and Perfect Graphs
inferredcites →https://doi.org/10.1109/43.293941openalex-snapshot
Exploiting the special structure of conflict and compatibility graphs in high-level synthesis
inferredcites →https://doi.org/10.1109/54.143143openalex-snapshot
DSS: a distributed high-level synthesis system
inferredcites →https://doi.org/10.1109/iccad.1990.129895openalex-snapshot
Exploiting the special structure of conflict and compatibility graphs in high-level synthesis
inferredcites →https://doi.org/10.1109/icvd.1996.489484openalex-snapshot
Synchronous controller models for synthesis from communicating VHDL processes
inferredcites →https://doi.org/10.1109/tcad.1986.1270207openalex-snapshot
Automated Synthesis of Data Paths in Digital Systems
inferredcites →https://doi.org/10.1145/157485.164667openalex-snapshot
Experiences in functional validation of a high level synthesis system
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/bfb0055125openalex-snapshot
Theorem Proving in Higher Order Logics
inferred← citeshttps://doi.org/10.1023/a:1008777509016openalex-snapshot
Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs
inferred← citeshttps://doi.org/10.1023/a:1011250531814openalex-snapshot
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/date.1999.761126openalex-snapshot
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
inferred← citeshttps://doi.org/10.1109/hldvt.2000.889564openalex-snapshot
An approach to high-level synthesis system validation using formally verified transformations
inferred← citeshttps://doi.org/10.1109/iccd.1998.727079openalex-snapshot
Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis
inferred← citeshttps://doi.org/10.1109/naecon.2008.4806561openalex-snapshot
Safety-Centric Design of Distributed Embedded Avionics
inferred← citeshttps://doi.org/10.1145/307418.307493openalex-snapshot
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.