On the public citation graph
Implementation issues about the embedding of existing high level synthesis algorithms in HOL
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-58450-1_50openalex-snapshot
An engineering approach to formal digital system design
inferredcites →https://doi.org/10.1007/3-540-60275-5_63openalex-snapshot
An automata theory dedicated towards formal circuit synthesis
inferredcites →https://doi.org/10.1007/3-540-63475-4openalex-snapshot
Formal Hardware Verification: Methods and Systems in Comparison
inferredcites →https://doi.org/10.1007/bf00121125openalex-snapshot
Formal hardware verification methods: A survey
inferredcites →https://doi.org/10.1017/cbo9780511569845openalex-snapshot
Higher Order Logic and Hardware Verification
inferredcites →https://doi.org/10.1109/43.31522openalex-snapshot
Force-directed scheduling for the behavioral synthesis of ASICs
inferredcites →https://doi.org/10.1145/127601.127751openalex-snapshot
Empirical evaluation of some high-level synthesis scheduling heuristics
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/3-540-44798-9_19openalex-snapshot
Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques
inferred← citeshttps://doi.org/10.1007/3-540-48153-2_15openalex-snapshot
Formal Synthesis at the Algorithmic Level
inferred← citeshttps://doi.org/10.1007/3-540-49519-3_16openalex-snapshot
Combined Formal Post- and Presynthesis Verification in High Level Synthesis
inferred← citeshttps://doi.org/10.1007/bfb0031817openalex-snapshot
Formal synthesis in circuit design — A classification and survey
inferred← citeshttps://doi.org/10.1007/bfb0055147openalex-snapshot
On the effectiveness of theorem proving guided discovery of formal assertions for a register allocator in a high-level synthesis system
inferred← citeshttps://doi.org/10.1007/bfb0105392openalex-snapshot
Theorem Proving in Higher Order Logics
inferred← citeshttps://doi.org/10.1023/a:1011250531814openalex-snapshot
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/eurmic.1998.711771openalex-snapshot
Performing high-level synthesis via program transformations within a theorem prover
inferred← citeshttps://doi.org/10.1109/hldvt.2000.889564openalex-snapshot
An approach to high-level synthesis system validation using formally verified transformations
inferred← citeshttps://doi.org/10.1109/iccd.1998.727079openalex-snapshot
Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis
inferred← citeshttps://doi.org/10.5555/261693.261699openalex-snapshot
An efficient representation for formal synthesis
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