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Pebble: A language for parametrised and reconfigurable hardware design
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-61730-2_18openalex-snapshot
The Trianus system and its application to custom computing
inferredcites →https://doi.org/10.1007/3-540-61730-2_3openalex-snapshot
A framework for developing parametrised FPGA libraries
inferredcites →https://doi.org/10.1007/3-540-63465-7_216openalex-snapshot
Pipeline morphing and virtual pipelines
inferredcites →https://doi.org/10.1016/0167-9260(93)90014-4openalex-snapshot
Systematic serialisation of array-based architectures
inferredcites →https://doi.org/10.1109/92.532038openalex-snapshot
A simulation tool for dynamically reconfigurable field programmable gate arrays
inferredcites →https://doi.org/10.1109/aspdac.1995.486388openalex-snapshot
HML: an innovative hardware description language and its translation to VHDL
inferredcites →https://doi.org/10.1109/fpga.1997.624605openalex-snapshot
Compilation tools for run-time reconfigurable designs
inferredcites →https://doi.org/10.1109/fpga.1997.624616openalex-snapshot
High level compilation for fine grained FPGAs
inferredcites →https://doi.org/10.1109/fpga.1998.707895openalex-snapshot
JHDL-an HDL for reconfigurable systems
inferredcites →https://doi.org/10.21236/ada450477openalex-snapshot
JHDL - An HDL for Reconfigurable Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/1-4020-3128-9_13openalex-snapshot
Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements Tools and a Case Study
inferred← citeshttps://doi.org/10.1007/3-540-36126-x_21openalex-snapshot
Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries
inferred← citeshttps://doi.org/10.1007/3-540-44614-1_64openalex-snapshot
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
inferred← citeshttps://doi.org/10.1007/3-540-44614-1_68openalex-snapshot
Combining Serialisation and Reconfiguration for FPGA Designs
inferred← citeshttps://doi.org/10.1007/3-540-44614-1_87openalex-snapshot
On Applying Software Development Best Practice to FPGAs in Safety-Critical Systems
inferred← citeshttps://doi.org/10.1007/3-540-44798-9_19openalex-snapshot
Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques
inferred← citeshttps://doi.org/10.1007/3-540-46117-5_40openalex-snapshot
Fly — A Modifiable Hardware Compiler
inferred← citeshttps://doi.org/10.1007/3-540-46117-5_55openalex-snapshot
Automating Customisation of Floating-Point Designs
inferred← citeshttps://doi.org/10.1007/3-540-48046-3_7openalex-snapshot
Language Issues of Compiling Ada to Hardware
inferred← citeshttps://doi.org/10.1007/978-3-319-01857-7_47openalex-snapshot
A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing
inferred← citeshttps://doi.org/10.1007/978-3-540-48302-1_19openalex-snapshot
Serial Hardware Libraries for Reconfigurable Designs
inferred← citeshttps://doi.org/10.1007/978-3-540-48302-1_40openalex-snapshot
SL – A Structural Hardware Design Language
inferred← citeshttps://doi.org/10.1007/978-90-481-3485-4_7openalex-snapshot
PolyDyn—Object-Oriented Modelling and Synthesis Targeting Dynamically Reconfigurable FPGAs
inferred← citeshttps://doi.org/10.1007/bfb0055244openalex-snapshot
A reconfigurable engine for real-time video processing
inferred← citeshttps://doi.org/10.1007/s00165-005-0075-8openalex-snapshot
Provably-correct hardware compilation tools based on pass separation techniques
inferred← citeshttps://doi.org/10.1007/s11227-005-0288-xopenalex-snapshot
Customisable Hardware Compilation
inferred← citeshttps://doi.org/10.1016/s1571-0661(05)80484-0openalex-snapshot
Refining Specifications to Programmable Logic
inferred← citeshttps://doi.org/10.1049/ip-cdt:20000486openalex-snapshot
Framework and tools for run-time reconfigurable designs
inferred← citeshttps://doi.org/10.1049/ip-cdt:20045086openalex-snapshot
Reconfigurable computing: architectures and design methods
inferred← citeshttps://doi.org/10.1109/92.920835openalex-snapshot
Object-oriented domain specific compilers for programming FPGAs
inferred← citeshttps://doi.org/10.1109/acssc.2000.910980openalex-snapshot
Perspectives on custom computing
inferred← citeshttps://doi.org/10.1109/date.2009.5090805openalex-snapshot
OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems
inferred← citeshttps://doi.org/10.1109/fpga.1999.803673openalex-snapshot
Debugging techniques for dynamically reconfigurable hardware
inferred← citeshttps://doi.org/10.1109/fpga.1999.803675openalex-snapshot
Reconfigurable computing for augmented reality
inferred← citeshttps://doi.org/10.1109/fpga.2000.903402openalex-snapshot
Automated extraction of run-time parameterisable cores from programmable device configurations
inferred← citeshttps://doi.org/10.1109/fpga.2002.1106662openalex-snapshot
PAM-Blox II: design and evaluation of C++ module generation for computing with FPGAs
inferred← citeshttps://doi.org/10.1109/fpga.2002.1106698openalex-snapshot
Customising floating-point designs
inferred← citeshttps://doi.org/10.1109/fpt.2002.1188663openalex-snapshot
Compiling run-time parametrisable designs
inferred← citeshttps://doi.org/10.1109/fpt.2002.1188723openalex-snapshot
Incremental programming for reconfigurable engines
inferred← citeshttps://doi.org/10.1109/fpt.2002.1188729openalex-snapshot
PD-XML: extensible markup language for processor description
inferred← citeshttps://doi.org/10.1109/fpt.2006.270297openalex-snapshot
Generating hardware from OpenMP programs
inferred← citeshttps://doi.org/10.1109/fpt.2007.4439239openalex-snapshot
Unifying FPGA Hardware Development
inferred← citeshttps://doi.org/10.1109/hicss.2003.1174812openalex-snapshot
Towards verifying parametrised hardware libraries with relative placement information [parametrised read parameterised]
inferred← citeshttps://doi.org/10.1109/hicss.2003.1174813openalex-snapshot
Combining imperative and declarative hardware descriptions
inferred← citeshttps://doi.org/10.1109/icassp.2001.941060openalex-snapshot
Parameterised floating-point arithmetic on FPGAs
inferred← citeshttps://doi.org/10.1109/icecs.2001.957532openalex-snapshot
A declarative framework for developing parametrised hardware libraries
inferred← citeshttps://doi.org/10.1109/ipdps.2003.1213326openalex-snapshot
Remote and partial reconfiguration of FPGAs: tools and trends
inferred← citeshttps://doi.org/10.1109/mwscas.2003.1562417openalex-snapshot
DiRAC: Dynamic Reconfiguration Animation and Control
inferred← citeshttps://doi.org/10.1109/rttas.2002.1137403openalex-snapshot
Hardware implementation of programming languages for real-time
inferred← citeshttps://doi.org/10.1109/tcad.2005.857377openalex-snapshot
ASC: a stream compiler for computing with FPGAs
inferred← citeshttps://doi.org/10.1117/12.2035385openalex-snapshot
Review of parallel computing methods and tools for FPGA technology
inferred← citeshttps://doi.org/10.1145/1081180.1081190openalex-snapshot
Developing critical systems with PLD components
inferred← citeshttps://doi.org/10.1145/1176760.1176773openalex-snapshot
Incremental elaboration for run-time reconfigurable hardware designs
inferred← citeshttps://doi.org/10.1145/2843946openalex-snapshot
A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing
inferred← citeshttps://doi.org/10.1145/502217.502233openalex-snapshot
Hardware compilation of sequential ada
inferred← citeshttps://doi.org/10.1145/503048.503068openalex-snapshot
Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series
inferred← citeshttps://doi.org/10.1145/581630.581641openalex-snapshot
Hardware implementation of the Ravenscar Ada tasking profile
inferred← citeshttps://doi.org/10.1145/584417.584430openalex-snapshot
Language issues of compiling Ada to hardware
inferred← citeshttps://doi.org/10.1145/611817.611871openalex-snapshot
FPGAs in critical hardware/software systems
inferred← citeshttps://doi.org/10.1145/774572.774587openalex-snapshot
Interface specification for reconfigurable components
inferred← citeshttps://doi.org/10.1145/993396.993399openalex-snapshot
A design flow for partially reconfigurable hardware
inferred← citeshttps://doi.org/10.1155/2008/738174openalex-snapshot
Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration
inferred← citeshttps://doi.org/10.1155/2012/504815openalex-snapshot
Occam-pi for Programming of Massively Parallel Reconfigurable Architectures
inferred← citeshttps://doi.org/10.21236/ada493427openalex-snapshot
High-Performance 3D Image Processing Architectures for Image-Guided Interventions
inferred← citeshttps://doi.org/10.26190/unsworks/16104openalex-snapshot
Configuration encoding techniques for fast FPGA reconfiguration
inferred← citeshttps://doi.org/10.5555/1874620.1874857openalex-snapshot
OSSS+R: a framework for application level modelling and synthesis of reconfigurable systems
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