On the public citation graph
A reconfigurable engine for real-time video processing
0 signed · 27 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-60294-1_99openalex-snapshot
A configurable logic processor for machine vision
inferredcites →https://doi.org/10.1007/3-540-61730-2_3openalex-snapshot
A framework for developing parametrised FPGA libraries
inferredcites →https://doi.org/10.1007/3-540-63465-7_211openalex-snapshot
The XC620ODS development system
inferredcites →https://doi.org/10.1007/3-540-63465-7_216openalex-snapshot
Pipeline morphing and virtual pipelines
inferredcites →https://doi.org/10.1007/3-540-63465-7_244openalex-snapshot
A reconfigurable coprocessor for a PCI-based real time computer vision system
inferredcites →https://doi.org/10.1007/bf00936948openalex-snapshot
Constructing hardware-software systems from a single description
inferredcites →https://doi.org/10.1007/bfb0055228openalex-snapshot
Pebble: A language for parametrised and reconfigurable hardware design
inferredcites →https://doi.org/10.1109/2.347995openalex-snapshot
Real-time image processing on a custom computing platform
inferredcites →https://doi.org/10.1109/fpga.1996.564815openalex-snapshot
Modelling and optimising run-time reconfigurable systems
inferredcites →https://doi.org/10.1109/fpga.1997.624605openalex-snapshot
Compilation tools for run-time reconfigurable designs
inferredcites →https://doi.org/10.1109/fpga.1998.707901openalex-snapshot
Accelerating Adobe Photoshop with reconfigurable logic
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11780519_32openalex-snapshot
ChipVision2 – A Stereo Vision System for Robots Based on Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1007/3-540-46117-5_56openalex-snapshot
Energy-Efficient Matrix Multiplication on FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-540-48302-1_34openalex-snapshot
An FPGA-Based Prototyping System for Real-Time Verification of Video Processing Schemes
inferred← citeshttps://doi.org/10.1007/bfb0055226openalex-snapshot
Field-Programmable Logic and Applications From FPGAs to Computing Paradigm
inferred← citeshttps://doi.org/10.1016/b978-012170960-0/50029-3openalex-snapshot
Configurable Computing
inferred← citeshttps://doi.org/10.1049/ip-cdt:20000486openalex-snapshot
Framework and tools for run-time reconfigurable designs
inferred← citeshttps://doi.org/10.1109/camp.2003.1598172openalex-snapshot
A Reconfigurable High Level FPGA-Based Coprocessor
inferred← citeshttps://doi.org/10.1109/fpga.1999.803675openalex-snapshot
Reconfigurable computing for augmented reality
inferred← citeshttps://doi.org/10.1109/fpt.2002.1188669openalex-snapshot
Area and time efficient implementations of matrix multiplication on FPGAs
inferred← citeshttps://doi.org/10.1109/iccsnt.2012.6525962openalex-snapshot
Real-time multiple video streams processing on PC-based FPGA platform
inferred← citeshttps://doi.org/10.1109/iswc.2004.31openalex-snapshot
Mobile Hand Tracking Using FPGAs for Low Powered Augmented Reality
inferred← citeshttps://doi.org/10.1109/iwrsp.2002.1029739openalex-snapshot
Benefits of macro-based multi-FPGA partitioning for video processing applications
inferred← citeshttps://doi.org/10.25560/1412openalex-snapshot
Video Processing Acceleration using Reconfigurable Logic and Graphics Processors
inferred← citeshttps://doi.org/10.48456/tr-824openalex-snapshot
Hardware synthesis from a stream-processing functional language
inferred← citeshttps://doi.org/10.5772/7126openalex-snapshot
Design of Embedded Augmented Reality Systems
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