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Discrete-time Promela and Spin

https://doi.org/10.1007/bfb0055359
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-52148-8_17openalex-snapshot
Timing assumptions and verification of finite-state concurrent systems
inferredcites →https://doi.org/10.1007/3-540-55719-9_103openalex-snapshot
What good are digital clocks?
inferredcites →https://doi.org/10.1007/3-540-61042-1_53openalex-snapshot
Extending promela and spin for real time
inferredcites →https://doi.org/10.1007/3-540-63165-8_213openalex-snapshot
Discrete-time control for rectangular hybrid automata
inferredcites →https://doi.org/10.1007/3-540-63166-6_47openalex-snapshot
Uppaal: Status & developments
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A bounded retransmission protocol for large data packets
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Timing analysis in COSPAN
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Abstraction in real time process algebra
inferredcites →https://doi.org/10.1007/bfb0035403openalex-snapshot
The bounded retransmission protocol must be on time!
inferredcites →https://doi.org/10.1007/bfb0055359openalex-snapshot
Discrete-time Promela and Spin
inferredcites →https://doi.org/10.1016/0304-3975(94)90010-8openalex-snapshot
A theory of timed automata
inferredcites →https://doi.org/10.1016/s1571-0661(05)80425-6openalex-snapshot
The bounded retransmission protocol revisited
inferredcites →https://doi.org/10.1145/122419.1024051openalex-snapshot
Book Review: Design and Validation of Computer Protocols by Gerard J. Holzmann (Prentice Hall, 1991)
inferredcites →https://doi.org/10.6100/ir408754openalex-snapshot
Models and axioms for a fragment of real time process algebra

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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A practical use of model checking for synthesis: generating a dam controller for flood management
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A Timing Analysis of AODV
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A Finite State Modeling of AFDX Frame Management Using Spin
inferred← citeshttps://doi.org/10.1007/978-3-540-73370-6_14openalex-snapshot
A SystemC/TLM Semantics in Promela and Its Possible Applications
inferred← citeshttps://doi.org/10.1007/978-3-540-75596-8_21openalex-snapshot
Timeout and Calendar Based Finite State Modeling and Verification of Real-Time Systems
inferred← citeshttps://doi.org/10.1007/978-3-540-79707-4_9openalex-snapshot
Computing Worst-Case Response Times in Real-Time Avionics Applications
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Fehlertoleranzanalyse des FlexRay Startup-Prozesses
inferred← citeshttps://doi.org/10.1007/978-3-642-04570-7_20openalex-snapshot
Developing a Decision Support Tool for Dam Management with SPIN
inferred← citeshttps://doi.org/10.1007/978-3-8348-9703-9openalex-snapshot
Eigenschaftsorientierte Beschreibung der logischen Architektur eingebetteter Systeme
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Norms and value based reasoning: justifying compliance and violation
inferred← citeshttps://doi.org/10.1007/s11036-017-0903-0openalex-snapshot
Formal Analysis of the PKMv3 Protocol
inferred← citeshttps://doi.org/10.1016/s0736-5845(00)00027-2openalex-snapshot
Automatic verification of a manufacturing system
inferred← citeshttps://doi.org/10.1049/iet-sen.2009.0043openalex-snapshot
Design tool to express failure detection protocols
inferred← citeshttps://doi.org/10.1109/access.2017.2685238openalex-snapshot
Applying Automated Model Extraction for Simulation and Verification of Real-Life SDL Specification With Spin
inferred← citeshttps://doi.org/10.1109/apsec.2006.56openalex-snapshot
Timing Verification of UML Activity Diagram Based Code Block Level Models for Real Time Multiprocessor System-on-Chip Applications
inferred← citeshttps://doi.org/10.1109/contel.2005.185973openalex-snapshot
Toward automatic generation of promela models from SDL specification
inferred← citeshttps://doi.org/10.1109/iccta.2007.4openalex-snapshot
A Finite State Analysis of Time-Triggered CAN (TTCAN) Protocol Using Spin
inferred← citeshttps://doi.org/10.1109/seaa.2009.53openalex-snapshot
Formal Semantics of the ProCom Real-Time Component Model
inferred← citeshttps://doi.org/10.1109/wfcs.2017.7991964openalex-snapshot
Model-based design languages: A case study
inferred← citeshttps://doi.org/10.1145/2901378.2901388openalex-snapshot
Using DEv-PROMELA for Modelling and Verification of Software
inferred← citeshttps://doi.org/10.1201/b17545-46openalex-snapshot
Model Checking
inferred← citeshttps://doi.org/10.31577/cai_2020_5_1022openalex-snapshot
Formal Verification of UML MARTE Specifications Based on a True Concurrency Real Time Model
inferred← citeshttps://doi.org/10.3233/978-1-61499-726-9-43openalex-snapshot
When and How to Violate Norms
inferred← citeshttps://doi.org/10.3233/fun-2008-851-428openalex-snapshot
Translation of Timed Promela to Timed Automata with Discrete Data
inferred← citeshttps://doi.org/10.3390/app12062990openalex-snapshot
Discrete Time Model for Process Meta Language with Fictitious-Clock
inferred← citeshttps://doi.org/10.4018/978-1-60566-182-7.ch008openalex-snapshot
Failure Detection Protocols in the Application Layer
inferred← citeshttps://doi.org/10.48550/arxiv.1008.1417openalex-snapshot
A Simplification of a Real-Time Verification Problem
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Formal specification and analysis of industrial systems
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