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Mechanizing verification of arithmetic circuits: SRT division

https://doi.org/10.1007/bfb0058026
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-56393-8_28openalex-snapshot
Implementing contextual rewriting
inferredcites →https://doi.org/10.1007/3-540-61474-5_62openalex-snapshot
Verifying the SRT division algorithm using theorem proving techniques
inferredcites →https://doi.org/10.1007/3-540-61474-5_63openalex-snapshot
Modular verification of SRT division
inferredcites →https://doi.org/10.1007/3-540-61474-5_64openalex-snapshot
Mechanically verifying a family of multiplier circuits
inferredcites →https://doi.org/10.1007/3-540-61511-3_112openalex-snapshot
Lemma discovery in automating induction
inferredcites →https://doi.org/10.1007/bf01383955openalex-snapshot
A proof of the nonrestoring division algorithm and its implementation on an ALU
inferredcites →https://doi.org/10.1007/bfb0012831openalex-snapshot
A mechanizable induction principle for equational specifications
inferredcites →https://doi.org/10.1007/bfb0028393openalex-snapshot
Rewriting, decision procedures and lemma speculation for automated hardware verification
inferredcites →https://doi.org/10.1007/bfb0031800openalex-snapshot
Verification of IEEE compliant subtractive division algorithms
inferredcites →https://doi.org/10.1016/0898-1221(94)00218-aopenalex-snapshot
An overview of Rewrite Rule Laboratory (RRL)
inferredcites →https://doi.org/10.1023/a:1008665528003openalex-snapshot
Verifying the SRT Division Algorithm Using Theorem Proving Techniques
inferredcites →https://doi.org/10.1093/qjmam/11.3.364openalex-snapshot
TECHNIQUES OF MULTIPLICATION AND DIVISION FOR AUTOMATIC BINARY COMPUTERS
inferredcites →https://doi.org/10.1109/arith.1981.6159293openalex-snapshot
Compatible hardware for division and square root
inferredcites →https://doi.org/10.1109/arith.1991.145561openalex-snapshot
A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages
inferredcites →https://doi.org/10.1109/dac.1996.545657openalex-snapshot
Bit-level analysis of an SRT divider circuit
inferredcites →https://doi.org/10.1109/iccd.1995.528918openalex-snapshot
Verification of a subtractive radix-2 square root algorithm and implementation
inferredcites →https://doi.org/10.1109/tec.1958.5222579openalex-snapshot
A New Class of Digital Division Methods
inferredcites →https://doi.org/10.21236/ada294842openalex-snapshot
Bit-Level Analysis of an SRT Divider Circuit.

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/10721959_26openalex-snapshot
Extending Decision Procedures with Induction Schemes
inferred← citeshttps://doi.org/10.1007/3-540-44798-9_26openalex-snapshot
Formal Verification of the VAMP Floating Point Unit
inferred← citeshttps://doi.org/10.1007/978-1-4419-1539-9_2openalex-snapshot
A Mechanically Verified Commercial SRT Divider
inferred← citeshttps://doi.org/10.1007/s10703-005-1613-yopenalex-snapshot
Formal Verification of the VAMP Floating Point Unit
inferred← citeshttps://doi.org/10.1109/aspdac.2002.994914openalex-snapshot
Register transfer operation analysis during data path verification
inferred← citeshttps://doi.org/10.1109/icvd.2000.812587openalex-snapshot
Status condition analysis during data path verification of sequential circuits
inferred← citeshttps://doi.org/10.1109/sbcci.2003.1232830openalex-snapshot
Modeling a reconfigurable system for computing the FFT in place via rewriting-logic
inferred← citeshttps://doi.org/10.1109/sccc.2003.1245446openalex-snapshot
Efficient computation of algebraic operations over dynamically reconfigurable systems specified by rewriting-logic environments
inferred← citeshttps://doi.org/10.1109/tc.2012.40openalex-snapshot
Computation and Formal Verification of SRT Quotient and Square Root Digit Selection Tables
inferred← citeshttps://doi.org/10.1145/1016568.1016634openalex-snapshot
Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic
inferred← citeshttps://doi.org/10.1145/1142155.1142156openalex-snapshot
Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic
inferred← citeshttps://doi.org/10.1145/1150343.1150379openalex-snapshot
SAEPTUM
inferred← citeshttps://doi.org/10.22028/d291-25704openalex-snapshot
Formal verification of a fully IEEE compliant floating point unit
inferred← citeshttps://doi.org/10.5555/832284.835467openalex-snapshot
Register Transfer Operation Analysis during Data Path Verification
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