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A proof of the nonrestoring division algorithm and its implementation on an ALU

https://doi.org/10.1007/bf01383955
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-57960-5openalex-snapshot
FM8501: A Verified Microprocessor
inferredcites →https://doi.org/10.1007/978-1-4613-2007-4_2openalex-snapshot
A Proof of Correctness of the Viper Microprocessor: The First Level
inferredcites →https://doi.org/10.1016/0378-4754(89)90181-xopenalex-snapshot
A computational logic handbook
inferredcites →https://doi.org/10.1109/dac.1986.1586171openalex-snapshot
An Intelligent Module Generator Environment
inferredcites →https://doi.org/10.1109/edac.1990.136621openalex-snapshot
Correctness proofs of parameterized hardware modules in the Cathedral-II synthesis environment
inferredcites →https://doi.org/10.1109/glsv.1992.218365openalex-snapshot
Models for bit-true simulation and high-level synthesis of DSP applications
inferredcites →https://doi.org/10.1109/mdt.1985.294883openalex-snapshot
IEEE Design & Test of Computers
inferredcites →https://doi.org/10.1109/mdt.1986.295047openalex-snapshot
Cathedral-II: A Silicon Compiler for Digital Signal Processing
inferredcites →https://doi.org/10.5555/949970.949985openalex-snapshot
Correctness proofs of parameterized hardware modules in the Cathedral-II synthesis environment

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/3-540-44798-9_26openalex-snapshot
Formal Verification of the VAMP Floating Point Unit
inferred← citeshttps://doi.org/10.1007/3-540-59047-1_42openalex-snapshot
Non-restoring integer square root: A case study in design by principled optimization
inferred← citeshttps://doi.org/10.1007/3-540-60045-0_35openalex-snapshot
Multipliers and dividers: Insights on arithmetic circuit verification (extended abstract)
inferred← citeshttps://doi.org/10.1007/3-540-61474-5_62openalex-snapshot
Verifying the SRT division algorithm using theorem proving techniques
inferred← citeshttps://doi.org/10.1007/3-540-61474-5_63openalex-snapshot
Modular verification of SRT division
inferred← citeshttps://doi.org/10.1007/978-3-642-58322-3_24openalex-snapshot
Proving the Correctness of a Complete Microprocessor
inferred← citeshttps://doi.org/10.1007/bfb0031797openalex-snapshot
Verification of all circuits in a floating-point unit using word-level model checking
inferred← citeshttps://doi.org/10.1007/bfb0031800openalex-snapshot
Verification of IEEE compliant subtractive division algorithms
inferred← citeshttps://doi.org/10.1007/bfb0058026openalex-snapshot
Mechanizing verification of arithmetic circuits: SRT division
inferred← citeshttps://doi.org/10.1007/s10703-005-1613-yopenalex-snapshot
Formal Verification of the VAMP Floating Point Unit
inferred← citeshttps://doi.org/10.1023/a:1008617612073openalex-snapshot
Modular Verification of SRT Division
inferred← citeshttps://doi.org/10.1023/a:1008665528003openalex-snapshot
Verifying the SRT Division Algorithm Using Theorem Proving Techniques
inferred← citeshttps://doi.org/10.1109/dac.1996.545657openalex-snapshot
Bit-level analysis of an SRT divider circuit
inferred← citeshttps://doi.org/10.1109/iccad.1995.479878openalex-snapshot
The formal verification of a pipelined double-precision IEEE floating-point multiplier
inferred← citeshttps://doi.org/10.1109/iccad.1996.569822openalex-snapshot
ACV: an arithmetic circuit verifier
inferred← citeshttps://doi.org/10.1109/iccd.1995.528918openalex-snapshot
Verification of a subtractive radix-2 square root algorithm and implementation
inferred← citeshttps://doi.org/10.1145/240518.240643openalex-snapshot
Bit-level analysis of an SRT divider circuit
inferred← citeshttps://doi.org/10.18260/1-2--11927openalex-snapshot
Integrating Formal Verification Into An Advanced Computer Architecture Course
inferred← citeshttps://doi.org/10.21236/ada294842openalex-snapshot
Bit-Level Analysis of an SRT Divider Circuit.
inferred← citeshttps://doi.org/10.22028/d291-25704openalex-snapshot
Formal verification of a fully IEEE compliant floating point unit
inferred← citeshttps://doi.org/10.5555/224841.224851openalex-snapshot
The formal verification of a pipelined double-precision IEEE floating-point multiplier
inferred← citeshttps://doi.org/10.5555/244522.244833openalex-snapshot
ACV: an arithmetic circuit verifier
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