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Reducing memory traffic via redundant store instructions
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/isca.1994.288147openalex-snapshot
A performance study of software and hardware data prefetching schemes
inferredcites →https://doi.org/10.1145/106972.106980openalex-snapshot
High-bandwidth data memory systems for superscalar processors
inferredcites →https://doi.org/10.1145/191995.192030openalex-snapshot
A performance study of software and hardware data prefetching schemes
inferredcites →https://doi.org/10.1145/232973.232983openalex-snapshot
Memory bandwidth limitations of future microprocessors
inferredcites →https://doi.org/10.1145/263580.263631openalex-snapshot
Speculative execution via address prediction and data prefetching
inferredcites →https://doi.org/10.1145/285930.285984openalex-snapshot
Using cache memory to reduce processor-memory traffic
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/325164.325162openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1145/800046.801647openalex-snapshot
Using cache memory to reduce processor-memory traffic
inferredcites →https://doi.org/10.5555/266800.266833openalex-snapshot
Cache sensitive module scheduling
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.future.2018.12.048openalex-snapshot
Efficient live virtual machine migration for memory write-intensive workloads
inferred← citeshttps://doi.org/10.1109/12.966493openalex-snapshot
Silent stores and store value locality
inferred← citeshttps://doi.org/10.1109/5.964442openalex-snapshot
Dynamic techniques for load and load-use scheduling
inferred← citeshttps://doi.org/10.1109/dsd.2014.108openalex-snapshot
Properties of Dynamically Dead Instructions for Contemporary Architectures
inferred← citeshttps://doi.org/10.1109/isca.2000.854389openalex-snapshot
On the value locality of store instructions
inferred← citeshttps://doi.org/10.1109/isca.2002.1003580openalex-snapshot
Implementing optimizations at decode time
inferred← citeshttps://doi.org/10.1109/micro.2000.898077openalex-snapshot
A study of slipstream processors
inferred← citeshttps://doi.org/10.1109/pact.2000.888338openalex-snapshot
Characterization of silent stores
inferred← citeshttps://doi.org/10.1109/tc.2024.3441835openalex-snapshot
A Parallel Tag Cache for Hardware Managed Tagged Memory in Multicore Processors
inferred← citeshttps://doi.org/10.1145/2567931openalex-snapshot
On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches
inferred← citeshttps://doi.org/10.1145/339647.339678openalex-snapshot
On the value locality of store instructions
inferred← citeshttps://doi.org/10.1145/360128.360155openalex-snapshot
A study of slipstream processors
inferred← citeshttps://doi.org/10.1145/545214.545240openalex-snapshot
Implementing optimizations at decode time
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93303openalex-snapshot
Microarchitectural Techniques to Exploit Repetitive Computations and Values
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