On the public citation graph
Systolic arrays: how to choose them
0 signed · 25 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf02253685openalex-snapshot
Spacetime representations of computational structures
inferredcites →https://doi.org/10.1109/12.16505openalex-snapshot
Optimal matrix multiplication on fault-tolerant VLSI arrays
inferredcites →https://doi.org/10.1109/12.21135openalex-snapshot
On mapping algorithms to linear and fault-tolerant systolic arrays
inferredcites →https://doi.org/10.1109/4.291openalex-snapshot
A comparison of systolic architectures for matrix multiplication
inferredcites →https://doi.org/10.1109/arrays.1988.18069openalex-snapshot
Mapping strategy for automatic design of systolic arrays
inferredcites →https://doi.org/10.1109/jssc.1984.1052128openalex-snapshot
Delay time and signal propagation in large-scale integrated circuits
inferredcites →https://doi.org/10.1109/mc.1987.1663624openalex-snapshot
Systolic Arrays: A Survey of Seven Projects
inferredcites →https://doi.org/10.1109/proc.1983.12532openalex-snapshot
On the design of algorithms for VLSI systolic arrays
inferredcites →https://doi.org/10.1109/tc.1985.1676516openalex-snapshot
The Design of Optimal Systolic Arrays
inferredcites →https://doi.org/10.1109/tc.1986.1676700openalex-snapshot
Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays
inferredcites →https://doi.org/10.25549/usctheses-c30-499818openalex-snapshot
Algorithm transformations for parallel processing and VLSI architecture design
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/bf02106828openalex-snapshot
Design techniques for fault-tolerant systolic arrays
inferred← citeshttps://doi.org/10.1016/0898-1221(96)00100-9openalex-snapshot
Designing of processor-time optimal systolic arrays for band matrix-vector multiplication
inferred← citeshttps://doi.org/10.1016/s0898-1221(97)00028-xopenalex-snapshot
The design of optimal planar systolic arrays for matrix multiplication
inferred← citeshttps://doi.org/10.1109/82.933810openalex-snapshot
Some space considerations of VLSI systolic array mappings
inferred← citeshttps://doi.org/10.1109/92.311644openalex-snapshot
Determining objective functions in systolic array designs
inferred← citeshttps://doi.org/10.1109/icapp.1995.472164openalex-snapshot
Synthesis of systolic arrays from single assignment algorithm
inferred← citeshttps://doi.org/10.1109/icecce49384.2020.9179433openalex-snapshot
Mapping Signal Processing Algorithms Into The Systolic Arrays
inferred← citeshttps://doi.org/10.1109/icpads.2000.857720openalex-snapshot
Some space considerations of VLSI systolic array mappings
inferred← citeshttps://doi.org/10.1109/iscas.2006.1692942openalex-snapshot
Integer linear programming method for spatial temporal mapping of the Viterbi decoder
inferred← citeshttps://doi.org/10.1109/iti.2008.4588528openalex-snapshot
The importance of using the linear transformation matrix in determining the number of processing elements in 2-dimensional systolic array for the algorithm of matrix-matrix multiplication
inferred← citeshttps://doi.org/10.1109/iti.2009.5196166openalex-snapshot
An implementation of MacMahon's partition analysis in ordering the number of lattice points in convex polyhedron with examples for systolic arrays
inferred← citeshttps://doi.org/10.1109/tpds.2006.39openalex-snapshot
Processor array architectures for deep packet classification
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.