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Synchronization, coherence, and event ordering in multiprocessors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/mc.1985.1662920openalex-snapshot
Essential Issues in Multiprocessor Systems
inferredcites →https://doi.org/10.1109/tc.1978.1675013openalex-snapshot
A New Solution to Coherence Problems in Multicache Systems
inferredcites →https://doi.org/10.1109/tc.1979.1675439openalex-snapshot
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
inferredcites →https://doi.org/10.1109/tc.1980.1675676openalex-snapshot
High-Speed Multiprocessors and Compilation Techniques
inferredcites →https://doi.org/10.1109/tc.1983.1676201openalex-snapshot
The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer
inferredcites →https://doi.org/10.1145/17356.17406openalex-snapshot
Memory access buffering in multiprocessors
inferredcites →https://doi.org/10.1145/285930.285984openalex-snapshot
Using cache memory to reduce processor-memory traffic
inferredcites →https://doi.org/10.1145/30350.30377openalex-snapshot
Correct memory operation of cache-based multiprocessors
inferredcites →https://doi.org/10.1145/356810.356813openalex-snapshot
Experience Using Multiprocessor Systems—A Status Report
inferredcites →https://doi.org/10.1145/356901.356903openalex-snapshot
Concepts and Notations for Concurrent Programming
inferredcites →https://doi.org/10.1145/6513.6514openalex-snapshot
Cache coherence protocols: evaluation using a multiprocessor simulation model
inferredcites →https://doi.org/10.1145/800046.801647openalex-snapshot
Using cache memory to reduce processor-memory traffic
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/(sici)1097-024x(199708)27:8<929::aid-spe113>3.0.co;2-#openalex-snapshot
MILLIPEDE: Easy Parallel Programming in Available Distributed Environments
inferred← citeshttps://doi.org/10.1002/cpe.739openalex-snapshot
HA‐PSLS: a highly available parallel single‐level store system
inferred← citeshttps://doi.org/10.1002/scj.4690210504openalex-snapshot
Cache Storage Control under Multiprocessor Environment
inferred← citeshttps://doi.org/10.1007/0-387-24049-7_4openalex-snapshot
Extending Clustersim with MP And DSM Modules
inferred← citeshttps://doi.org/10.1007/11864219_18openalex-snapshot
On Consistency of Encrypted Files
inferred← citeshttps://doi.org/10.1007/3-540-44681-8_107openalex-snapshot
Smooth and Efficient Integration of High-Availability in a Parallel Single Level Store System
inferred← citeshttps://doi.org/10.1007/3-540-58430-7_38openalex-snapshot
A switch cache design for MIN-based shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1007/978-0-387-34047-0_10openalex-snapshot
How Is Bandwidth Used in Computers?
inferred← citeshttps://doi.org/10.1007/978-1-4612-3192-9_1openalex-snapshot
The Scalable Processor Architecture (SPARC)
inferred← citeshttps://doi.org/10.1007/978-1-4612-3192-9_2openalex-snapshot
The Scalable Processor Architecture (SPARC)
inferred← citeshttps://doi.org/10.1007/978-1-4612-3192-9_8openalex-snapshot
SPARC: An ASIC Solution for High-Performance Microprocessors
inferred← citeshttps://doi.org/10.1007/978-1-4612-3334-3_6openalex-snapshot
SPARC: Scalable Processor Architecture
inferred← citeshttps://doi.org/10.1007/978-1-4613-1537-7_7openalex-snapshot
Performance of Parallel Loops using Alternative Cache Consistency Protocols on a Non-Bus Multiprocessor
inferred← citeshttps://doi.org/10.1007/978-1-4613-3400-2_3openalex-snapshot
A Programmer’s View of Parallel Computers
inferred← citeshttps://doi.org/10.1007/978-1-4615-3604-8_13openalex-snapshot
The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor
inferred← citeshttps://doi.org/10.1007/978-1-4615-3604-8_2openalex-snapshot
Formal Specification of Memory Models
inferred← citeshttps://doi.org/10.1007/978-1-4615-3604-8_4openalex-snapshot
Locks, Directories, and Weak Coherence—a Recipe for Scalable Shared Memory Architectures
inferred← citeshttps://doi.org/10.1007/978-1-4615-3748-9_68openalex-snapshot
Data Bases, Knowledge Bases and Intelligent Information Systems
inferred← citeshttps://doi.org/10.1007/978-3-642-03095-6_7openalex-snapshot
A Software Transactional Memory Service for Grids
inferred← citeshttps://doi.org/10.1007/978-3-642-77422-5_28openalex-snapshot
Implementing Locks in Distributed-Memory Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-981-99-7339-2_27openalex-snapshot
Elevating Database Performance: Current Caching and Prefetching Strategies for Online Databases in Nigeria
inferred← citeshttps://doi.org/10.1007/bf01407863openalex-snapshot
Cache coherence requirements for interprocess rendezvous
inferred← citeshttps://doi.org/10.1007/bf02699885openalex-snapshot
Adaptive granularity: Transparent integration of fine- and coarse-grain communication
inferred← citeshttps://doi.org/10.1007/bf02946601openalex-snapshot
Out-of-order execution in sequentially consistent shared-memory systems: Theory and experiments
inferred← citeshttps://doi.org/10.1007/bf02995734openalex-snapshot
Protocoles simples pour ľimplémentation répartie des sémaphores
inferred← citeshttps://doi.org/10.1007/bfb0024735openalex-snapshot
A RISC approach to weak cache coherence
inferred← citeshttps://doi.org/10.1007/s004460050014openalex-snapshot
Implementing hybrid consistency with high-level synchronization operations
inferred← citeshttps://doi.org/10.1007/s41019-025-00342-6openalex-snapshot
Workload-Aware Buffer Prefetching for Database Systems
inferred← citeshttps://doi.org/10.1016/0020-0190(93)90083-lopenalex-snapshot
A simple correctness proof of the MCS contention-free lock
inferred← citeshttps://doi.org/10.1016/0141-9331(95)01060-2openalex-snapshot
The word-invalidate cache coherence protocol
inferred← citeshttps://doi.org/10.1016/0165-6074(93)90132-5openalex-snapshot
The memory hierarchy of the CHESS computer
inferred← citeshttps://doi.org/10.1016/0165-6074(95)99030-9openalex-snapshot
Mapping real-time motion estimation type algorithms to memory efficient, programmable multi-processor architectures
inferred← citeshttps://doi.org/10.1016/0166-5316(94)90014-0openalex-snapshot
Optimal task scheduling on distributed parallel processors
inferred← citeshttps://doi.org/10.1016/0167-739x(92)90017-6openalex-snapshot
SPARC: A scalable processor architecture
inferred← citeshttps://doi.org/10.1016/0306-4573(91)90084-yopenalex-snapshot
Network design for the implementation of text searching using a multicomputer
inferred← citeshttps://doi.org/10.1016/0360-8352(90)90103-sopenalex-snapshot
A new standard for industrial control languages
inferred← citeshttps://doi.org/10.1016/0743-7315(91)90014-zopenalex-snapshot
Tolerating latency through software-controlled prefetching in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1016/0743-7315(92)90048-ropenalex-snapshot
Notification and multicast networks for synchronization and coherence
inferred← citeshttps://doi.org/10.1016/b978-044482106-5/50017-xopenalex-snapshot
A Memory Efficient, Programmable Multi-Processor Architecture for Real-Time Motion Estimation Type Algorithms
inferred← citeshttps://doi.org/10.1016/s0065-2458(06)69001-3openalex-snapshot
The Architecture of Efficient Multi-Core Processors: A Holistic Approach
inferred← citeshttps://doi.org/10.1016/s0065-2458(08)60325-3openalex-snapshot
Parallel Computer Architectures
inferred← citeshttps://doi.org/10.1016/s0065-2458(08)60546-xopenalex-snapshot
Cache Coherence in Multiprocessors: A Survey
inferred← citeshttps://doi.org/10.1016/s1383-7621(99)00048-xopenalex-snapshot
Broadcast directory: A scalable cache coherent architecture for mesh-connected multiprocessors
inferred← citeshttps://doi.org/10.1109/12.755001openalex-snapshot
An efficient tree cache coherence protocol for distributed shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/12.954507openalex-snapshot
ADir/sub p/NB: a cost-effective way to implement full map directory-based cache coherence protocols
inferred← citeshttps://doi.org/10.1109/2.347997openalex-snapshot
RPM: a rapid prototyping engine for multiprocessor systems
inferred← citeshttps://doi.org/10.1109/2.53355openalex-snapshot
Algorithms implementing distributed shared memory
inferred← citeshttps://doi.org/10.1109/2.84877openalex-snapshot
Distributed shared memory: a survey of issues and algorithms
inferred← citeshttps://doi.org/10.1109/32.55094openalex-snapshot
Memory access dependencies in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1109/40.127582openalex-snapshot
Organization of the Motorola 88110 superscalar RISC microprocessor
inferred← citeshttps://doi.org/10.1109/40.216748openalex-snapshot
Sparcle: an evolutionary processor design for large-scale multiprocessors
inferred← citeshttps://doi.org/10.1109/40.272836openalex-snapshot
Evolution of the PowerPC architecture
inferred← citeshttps://doi.org/10.1109/40.331392openalex-snapshot
Hardware approaches to cache coherence in shared-memory multiprocessors. 2
inferred← citeshttps://doi.org/10.1109/5.476078openalex-snapshot
The microarchitecture of superscalar processors
inferred← citeshttps://doi.org/10.1109/54.706042openalex-snapshot
Rapid hardware prototyping on RPM-2
inferred← citeshttps://doi.org/10.1109/71.139202openalex-snapshot
Design of an adaptive cache coherence protocol for large scale multiprocessors
inferred← citeshttps://doi.org/10.1109/71.262587openalex-snapshot
Access graphs: a model for investigating memory consistency
inferred← citeshttps://doi.org/10.1109/71.285604openalex-snapshot
The impact of parallel loop scheduling strategies on prefetching in a shared memory multiprocessor
inferred← citeshttps://doi.org/10.1109/71.466631openalex-snapshot
Stack evaluation of arbitrary set-associative multiprocessor caches
inferred← citeshttps://doi.org/10.1109/71.780868openalex-snapshot
PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1109/71.80130openalex-snapshot
A distributed management scheme for partitionable parallel computers
inferred← citeshttps://doi.org/10.1109/71.80134openalex-snapshot
Error recovery in shared memory multiprocessors using private caches
inferred← citeshttps://doi.org/10.1109/acssc.1993.342629openalex-snapshot
Universal read/write buffer for multiprocessor cache coherency schemes
inferred← citeshttps://doi.org/10.1109/aspdac.1995.486379openalex-snapshot
Automatic verification of memory systems which service their requests out of order
inferred← citeshttps://doi.org/10.1109/cmpcon.1988.4874openalex-snapshot
The scalable processor architecture (SPARC)
inferred← citeshttps://doi.org/10.1109/cmpcon.1990.63713openalex-snapshot
MOPPS: a scheme for managing parallel scientific programs in a distributed architecture
inferred← citeshttps://doi.org/10.1109/cmpcon.1993.289647openalex-snapshot
Multiprocessing aspects of the PowerPC 601
inferred← citeshttps://doi.org/10.1109/comswa.2006.1665176openalex-snapshot
Maintaining Update-Linearizability for Replicated Information in MANETs
inferred← citeshttps://doi.org/10.1109/date.2001.915090openalex-snapshot
System-on-a-chip processor synchronization support in hardware
inferred← citeshttps://doi.org/10.1109/dmcc.1990.556268openalex-snapshot
Design and lmplementation of a Multi-Cache System on a Loosely Coupled Multiprocessor
inferred← citeshttps://doi.org/10.1109/dmcc.1991.633356openalex-snapshot
Benefits of Weak Coherence for Distributed shared Memory Systems
inferred← citeshttps://doi.org/10.1109/empdp.1995.389134openalex-snapshot
DIPC-a monitor for distributed inter-process communication
inferred← citeshttps://doi.org/10.1109/ftpds.1994.494478openalex-snapshot
Reliable processor coordination for distributed resource management in hypercubes
inferred← citeshttps://doi.org/10.1109/glocom.1996.591919openalex-snapshot
Path caching in connection-oriented networks
inferred← citeshttps://doi.org/10.1109/hicss.1991.183911openalex-snapshot
Experimental evaluation of multilevel caches for shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/hicss.1992.183195openalex-snapshot
An approach to dynamic software cache consistency maintenance based on conditional invalidation
inferred← citeshttps://doi.org/10.1109/hicss.1993.270604openalex-snapshot
A survey of hardware solutions for maintenance of cache coherence in shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/hicss.1994.323131openalex-snapshot
Fast locks in distributed shared memory systems
inferred← citeshttps://doi.org/10.1109/hicss.1994.323132openalex-snapshot
Adding fault-tolerance to algorithms for weak consistency
inferred← citeshttps://doi.org/10.1109/hicss.1995.375386openalex-snapshot
A survey of software solutions for maintenance of cache consistency in shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/hicss.1996.495453openalex-snapshot
Data prefetching for distributed shared memory systems
inferred← citeshttps://doi.org/10.1109/iccd.1994.331853openalex-snapshot
Analysis of multiprocessor memory reference behavior
inferred← citeshttps://doi.org/10.1109/icdcs.1990.89257openalex-snapshot
Real-time synchronization protocols for shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/icdcs.1992.235011openalex-snapshot
Type-specific coherence protocols for distributed shared memory
inferred← citeshttps://doi.org/10.1109/icdcs.1994.302435openalex-snapshot
Optimistic synchronization in distributed shared memory
inferred← citeshttps://doi.org/10.1109/icdcs.1995.500049openalex-snapshot
Implementing sequentially consistent shared objects using broadcast and point-to-point communication
inferred← citeshttps://doi.org/10.1109/icde.1992.213161openalex-snapshot
Transactions in distributed shared memory systems
inferred← citeshttps://doi.org/10.1109/icpads.1997.652571openalex-snapshot
Distributed shared memory on IBM SP2
inferred← citeshttps://doi.org/10.1109/icpp.1993.15openalex-snapshot
A Characterization of Scalable Shared Memories
inferred← citeshttps://doi.org/10.1109/icpp.1997.622672openalex-snapshot
False sharing elimination by selection of runtime scheduling parameters
inferred← citeshttps://doi.org/10.1109/ipps.1996.508037openalex-snapshot
The combined effectiveness of unimodular transformations, tiling, and software prefetching
inferred← citeshttps://doi.org/10.1109/isca.1989.714582openalex-snapshot
On Data Synchronization For Multiprocessors
inferred← citeshttps://doi.org/10.1109/isca.1990.134498openalex-snapshot
APRIL: a processor architecture for multiprocessing
inferred← citeshttps://doi.org/10.1109/isca.1990.134502openalex-snapshot
Weak ordering-a new definition
inferred← citeshttps://doi.org/10.1109/isca.1990.134504openalex-snapshot
Synchronization with multiprocessor caches
inferred← citeshttps://doi.org/10.1109/isca.1990.134515openalex-snapshot
Adaptive software cache management for distributed shared memory architectures
inferred← citeshttps://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferred← citeshttps://doi.org/10.1109/isca.2005.34openalex-snapshot
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
inferred← citeshttps://doi.org/10.1109/ispan.1997.645055openalex-snapshot
Critical sections and producer/consumer queues in weak memory systems
inferred← citeshttps://doi.org/10.1109/mm.2009.44openalex-snapshot
Maintaining I/O Data Coherence in Embedded Multicore Systems
inferred← citeshttps://doi.org/10.1109/mwscas.1993.343099openalex-snapshot
A hardware cache coherency scheme for multiprocessors
inferred← citeshttps://doi.org/10.1109/pact.1996.552556openalex-snapshot
Improving the effectiveness of software prefetching with adaptive executions
inferred← citeshttps://doi.org/10.1109/pact.1996.554034openalex-snapshot
Adaptive granularity: transparent integration of fine- and coarse-grain communication
inferred← citeshttps://doi.org/10.1109/real.2003.1253271openalex-snapshot
Hardware support for priority inheritance
inferred← citeshttps://doi.org/10.1109/secon.1990.117917openalex-snapshot
The multiprocessor system with a fairly weighted global bus arbitration circuit
inferred← citeshttps://doi.org/10.1109/simsym.1996.492151openalex-snapshot
Trojan: a high-performance simulator for shared memory architectures
inferred← citeshttps://doi.org/10.1109/spdp.1992.242725openalex-snapshot
A balanced layered allocation scheme for hypercube based dataflow systems
inferred← citeshttps://doi.org/10.1109/superc.1988.44632openalex-snapshot
A processor architecture for Horizon
inferred← citeshttps://doi.org/10.1109/superc.1990.130103openalex-snapshot
Future general purpose supercomputer architectures
inferred← citeshttps://doi.org/10.1109/superc.1992.236669openalex-snapshot
Willow: a scalable shared memory multiprocessor
inferred← citeshttps://doi.org/10.1111/j.1467-8667.1991.tb00397.xopenalex-snapshot
Developments in Multiprocessor Scheduling
inferred← citeshttps://doi.org/10.1137/s0097539794278396openalex-snapshot
Shared Memory Consistency Conditions for Nonsequential Execution: Definitions and Programming Strategies
inferred← citeshttps://doi.org/10.1145/1016540.1016566openalex-snapshot
A fully distributed architecture for massively multiplayer online games
inferred← citeshttps://doi.org/10.1145/1028176.1006711openalex-snapshot
Transactional Memory Coherence and Consistency
inferred← citeshttps://doi.org/10.1145/1065983.1066005openalex-snapshot
Using n-trees for scalable event ordering in peer-to-peer games
inferred← citeshttps://doi.org/10.1145/1080695.1070004openalex-snapshot
Interconnections in Multi-Core Architectures
inferred← citeshttps://doi.org/10.1145/113379.113407openalex-snapshot
Sequential consistency versus linearizability (extended abstract)
inferred← citeshttps://doi.org/10.1145/129712.129742openalex-snapshot
Efficient program transformations for resilient parallel computation via randomization (preliminary version)
inferred← citeshttps://doi.org/10.1145/129712.129778openalex-snapshot
A correctness condition for high-performance multiprocessors (extended abstract)
inferred← citeshttps://doi.org/10.1145/143369.143379openalex-snapshot
Characterizing memory performance in vector multiprocessors
inferred← citeshttps://doi.org/10.1145/151634.151639openalex-snapshot
Empirical performance evaluation of concurrency and coherency control protocols for database sharing systems
inferred← citeshttps://doi.org/10.1145/158439.158907openalex-snapshot
Cache coherence in large-scale shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1145/164051.164077openalex-snapshot
Implementing hybrid consistency with high-level synchronization operations
inferred← citeshttps://doi.org/10.1145/165231.165263openalex-snapshot
Shared memory consistency conditions for non-sequential execution
inferred← citeshttps://doi.org/10.1145/169627.169724openalex-snapshot
Parallel programming in Split-C
inferred← citeshttps://doi.org/10.1145/170791.170853openalex-snapshot
Data flow analysis for parallel programs
inferred← citeshttps://doi.org/10.1145/174130.174143openalex-snapshot
A performance evaluation of several priority policies for parallel processing systems
inferred← citeshttps://doi.org/10.1145/174666.174668openalex-snapshot
The interdisciplinary study of coordination
inferred← citeshttps://doi.org/10.1145/176575.176576openalex-snapshot
Sequential consistency versus linearizability
inferred← citeshttps://doi.org/10.1145/197917.197944openalex-snapshot
Making operations of concurrent data types fast
inferred← citeshttps://doi.org/10.1145/200836.200872openalex-snapshot
Bounds on the speedup and efficiency of partial synchronization in parallel processing systems
inferred← citeshttps://doi.org/10.1145/215399.215434openalex-snapshot
The communication requirements of mutual exclusion
inferred← citeshttps://doi.org/10.1145/218646.218651openalex-snapshot
A comprehensive bibliography of distributed shared memory
inferred← citeshttps://doi.org/10.1145/224170.224398openalex-snapshot
Lazy release consistency for hardware-coherent multiprocessors
inferred← citeshttps://doi.org/10.1145/271003.274463openalex-snapshot
Out-of-order execution in sequentially consistent shared-memory systems
inferred← citeshttps://doi.org/10.1145/271019.271027openalex-snapshot
An interaction of coherence protocols and memory consistency models in DSM systems
inferred← citeshttps://doi.org/10.1145/273011.273021openalex-snapshot
Tolerating latency in multiprocessors through compiler-inserted prefetching
inferred← citeshttps://doi.org/10.1145/273865.273884openalex-snapshot
Implementing sequentially consistent shared objects using broadcast and point-to-point communication
inferred← citeshttps://doi.org/10.1145/3166094.3166100openalex-snapshot
Adapting software applications to hybrid supercomputer
inferred← citeshttps://doi.org/10.1145/325096.325107openalex-snapshot
Synchronization with multiprocessor caches
inferred← citeshttps://doi.org/10.1145/325096.325124openalex-snapshot
Adaptive software cache management for distributed shared memory architectures
inferred← citeshttps://doi.org/10.1145/325164.325124openalex-snapshot
Adaptive software cache management for distributed shared memory architectures
inferred← citeshttps://doi.org/10.1145/332799.332800openalex-snapshot
A high-level abstraction of shared accesses
inferred← citeshttps://doi.org/10.1145/74925.74972openalex-snapshot
On data synchronization for multiprocessors
inferred← citeshttps://doi.org/10.1145/74926.74972openalex-snapshot
On data synchronization for multiprocessors
inferred← citeshttps://doi.org/10.1145/76263.76315openalex-snapshot
C2MP: a cache-coherent, distributed memory multiprocessor-system
inferred← citeshttps://doi.org/10.1145/96749.98249openalex-snapshot
Parallel text searching in serial files using a processor farm
inferred← citeshttps://doi.org/10.1145/99163.99182openalex-snapshot
Munin: distributed shared memory based on type-specific memory coherence
inferred← citeshttps://doi.org/10.1145/99164.99182openalex-snapshot
Munin: distributed shared memory based on type-specific memory coherence
inferred← citeshttps://doi.org/10.1147/rd.366.01001openalex-snapshot
Architecture, design, and performance of Application System/400 (AS/400) multiprocessors
inferred← citeshttps://doi.org/10.1177/109434208900300302openalex-snapshot
The Perfect Club Benchmarks: Effective Performance Evaluation of Supercomputers
inferred← citeshttps://doi.org/10.1260/1708-5284.10.3.283openalex-snapshot
Response compression in space with cascade of two-input linear and nonlinear logic
inferred← citeshttps://doi.org/10.1260/1708-5284.9.3.199openalex-snapshot
Cascade of two-input nonlinear logic in designing space compression networks in VLSI
inferred← citeshttps://doi.org/10.1287/opre.42.1.65openalex-snapshot
Parallel Simplex for Large Pure Network Problems: Computational Testing and Sources of Speedup
inferred← citeshttps://doi.org/10.18130/v3fc6dopenalex-snapshot
Maximizing Memory Bandwidth for Streamed Computations
inferred← citeshttps://doi.org/10.18419/opus-2600openalex-snapshot
Consistent data replication in mobile ad hoc networks
inferred← citeshttps://doi.org/10.21236/ada237476openalex-snapshot
APRIL: A Processor Architecture for Multiprocessing
inferred← citeshttps://doi.org/10.21236/ada237629openalex-snapshot
LimitLESS Directories: A Scalable Cache Coherence Scheme
inferred← citeshttps://doi.org/10.21236/ada341142openalex-snapshot
Concept of Operations for a Virtual Machine for C3I Applications.
inferred← citeshttps://doi.org/10.31274/rtd-180813-11532openalex-snapshot
A multiple-bus, active backplane architecture for multiprocessor systems
inferred← citeshttps://doi.org/10.31274/rtd-180813-9501openalex-snapshot
A logical layer protocol for ActiveBus architecture
inferred← citeshttps://doi.org/10.3166/tsi.30.809-839openalex-snapshot
Emulation de mémoire partagée en environnements distribués dynamiques
inferred← citeshttps://doi.org/10.3929/ethz-a-004453415openalex-snapshot
The active object system design and multiprocessor implementation
inferred← citeshttps://doi.org/10.4995/thesis/10251/6067openalex-snapshot
Arquitectura de un sistema C4ISR para pequeñas unidades.
inferred← citeshttps://doi.org/10.5555/1089053.1089104openalex-snapshot
Synchronization and cache coherence in computer design
inferred← citeshttps://doi.org/10.5555/110382.110611openalex-snapshot
Future general purpose supercomputer architectures
inferred← citeshttps://doi.org/10.5555/224659.224954openalex-snapshot
A proposal of self-cleanup cache
inferred← citeshttps://doi.org/10.5555/367072.367838openalex-snapshot
System-on-a-chip processor synchronization support in hardware
inferred← citeshttps://doi.org/10.6028/nist.ir.89-4053openalex-snapshot
Architecturally-focused benchmarks with a communication example
inferred← citeshttps://doi.org/10.6028/nist.ir.90-4251openalex-snapshot
Analysis of computational parallelism with a concurrent hierarchical robot control system
inferred← citeshttps://doi.org/10.70675/13b8dff9zb86dz461cz9050z2f8af14c953dopenalex-snapshot
Les objets ajustés : Une approche bien fondée et efficace pour la programmation concurrente
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