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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0141-9331(88)90091-9openalex-snapshot
A VLSI architecture for concurrent data structures
inferredcites →https://doi.org/10.1109/2.15openalex-snapshot
Synchronization, coherence, and event ordering in multiprocessors
inferredcites →https://doi.org/10.1109/2.55500openalex-snapshot
Directory-based cache coherence in large-scale multiprocessors
inferredcites →https://doi.org/10.1109/2.55503openalex-snapshot
Distributed-directory scheme: scalable coherent interface
inferredcites →https://doi.org/10.1109/71.86103openalex-snapshot
Lazy task creation: a technique for increasing the granularity of parallel programs
inferredcites →https://doi.org/10.1109/tc.1978.1675013openalex-snapshot
A New Solution to Coherence Problems in Multicache Systems
inferredcites →https://doi.org/10.1109/tc.1979.1675439openalex-snapshot
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
inferredcites →https://doi.org/10.1109/tc.1984.1676396openalex-snapshot
Concurrent VLSI Architectures
inferredcites →https://doi.org/10.1145/1499799.1499901openalex-snapshot
Cache system design in the tightly coupled multiprocessor system
inferredcites →https://doi.org/10.1145/17356.17399openalex-snapshot
Software-controlled caches in the VMP multiprocessor
inferredcites →https://doi.org/10.1145/285930.285984openalex-snapshot
Using cache memory to reduce processor-memory traffic
inferredcites →https://doi.org/10.1145/285930.285987openalex-snapshot
A low-overhead coherence solution for multiprocessors with private cache memories
inferredcites →https://doi.org/10.1145/285930.285995openalex-snapshot
An evaluation of directory schemes for cache coherence
inferredcites →https://doi.org/10.1145/285930.285997openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/325096.325124openalex-snapshot
Adaptive software cache management for distributed shared memory architectures
inferredcites →https://doi.org/10.1145/325096.325130openalex-snapshot
An empirical evaluation of two memory-efficient directory methods
inferredcites →https://doi.org/10.1145/325096.325132openalex-snapshot
The directory-based cache coherence protocol for the DASH multiprocessor
inferredcites →https://doi.org/10.1145/327070.327237openalex-snapshot
Implementing a cache consistency protocol
inferredcites →https://doi.org/10.1145/36204.36199openalex-snapshot
Firefly: a multiprocessor workstation
inferredcites →https://doi.org/10.1145/68182.68205openalex-snapshot
Analysis of cache invalidation patterns in multiprocessors
inferredcites →https://doi.org/10.1145/73141.74825openalex-snapshot
Mul-T: a high-performance parallel Lisp
inferredcites →https://doi.org/10.1145/773453.808205openalex-snapshot
An economical solution to the cache coherence problem
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A tale of two directories: implementing distributed shared objects in Java
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Shared Memory Multiprocessors
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Chip size and performance evaluations of shared cache for on‐chip multiprocessor
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Cache-Based Synchronization in Shared Memory Multiprocessors
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Evaluating the Performance of Multithreading and Prefetching in Multiprocessors
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SPEED DMON:Cache Coherence on an Optical Multichannel Interconnect Architecture
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Processor Mechanisms for Software Shard Memory
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SLiD — A cost-effective and Scalable Limited-Directory scheme for cache coherence
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Simulating the data diffusion machine
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Randomized Shared Memory—Concept and Efficiency of a Scalable Shared Memory Scheme
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Optimul: A hybrid multiprocessor for distributed and shared memory multiprocessing with WDM optical fiber interconnections
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Demand-based coscheduling of parallel jobs on multiprogrammed multiprocessors
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Performance Limits of Compiler-Directed Multiprocessor Cache Coherence Enforcement
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Multithreaded Architectures: Principles, Projects, and Issues
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The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor
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CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures
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A Scalable and Adaptive Directory Scheme for Hardware Distributed Shared Memory
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A Two-Level Directory Organization Solution for CC-NUMA Systems
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To Snoop or Not to Snoop: Evaluation of Fine-Grain and Coarse-Grain Snoop Filtering Techniques
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Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs
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Mechanisms for Parallel Computers
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Architectural Frontiers Enabled by High Connectivity Packaging
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Hierarchical clustering: A structure for scalable multiprocessor operating system design
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Scalable cache consistency for hierarchically structured multiprocessors
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An Empirical Evaluation of the Convex SPP-1000 Hierarchical Shared Memory System
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The arrow distributed directory protocol
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Energy-efficient hybrid coherence protocol for multicore processors
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DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures
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DASC-DIR: a low-overhead coherence directory for many-core processors
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PS directory: a scalable multilevel directory cache for CMPs
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Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study
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DEAM: Decoupled, Expressive, Area-Efficient Metadata Cache
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An initial evaluation of the Convex SPP-1000 for earth and space science applications
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Reduced interprocessor-communication architecture and its implementation on EM-4
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Hiding shared memory reference latency on the Galactica Net distributed shared memory architecture
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Hierarchical coherency management for shared virtual memory multicomputers
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Towards general and exact distributed invalidation
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Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors
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Single system image: A survey
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A comparative evaluation of hardware-only and software-only directory protocols in shared-memory multiprocessors
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A scalable organization for distributed directories
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Synergistic design of an application-oriented sparse directory on many-core embedded systems
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Virtual memory on data diffusion architectures
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Broadcast directory: A scalable cache coherent architecture for mesh-connected multiprocessors
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A quantitative analysis of the performance and scalability of distributed shared memory cache coherence protocols
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An efficient tree cache coherence protocol for distributed shared memory multiprocessors
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Sparcle: an evolutionary processor design for large-scale multiprocessors
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Hardware approaches to cache coherence in shared-memory multiprocessors. 2
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Performance tradeoffs in multithreaded processors
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The DASH prototype: Logic overhead and performance
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Improving memory utilization in cache coherence directories
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The potential of compile-time analysis to adapt the cache coherence enforcement strategy to the data sharing characteristics
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Lazy task creation: a technique for increasing the granularity of parallel programs
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Exploiting the advantages of object-based DSM in a heterogeneous cluster environment
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Adaptive Snoop Granularity and Transactional Snoop Filtering in Hardware Transactional Memory
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Anatomy of a Message in the Alewife Multiprocessor
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Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
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SigNet: Network-on-chip filtering for coarse vector directories
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The role of associative memory in virtual shared memory architectures: a price-performance comparison
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A multi-cache coherence scheme for shuffle-exchange network based multiprocessors
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A survey of hardware solutions for maintenance of cache coherence in shared memory multiprocessors
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Update-based cache coherence protocols for scalable shared-memory multiprocessors
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Simple COMA node implementations
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Stash directory: A scalable directory for many-core coherence
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Studying the impact of multicore processor scaling on directory techniques via reuse distance analysis
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Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking
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Tardis: Time Traveling Coherence Algorithm for Distributed Shared Memory
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An efficient single copy cache coherence protocol for multiprocessors with multistage interconnection networks
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Efficient, snoopless, System-on-Chip coherence
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Cache consistency in hierarchical-ring-based multiprocessors
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Efficient and scalable cache coherence schemes for shared memory hypercube multiprocessors
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Building Expressive and Area-Efficient Directories with Hybrid Representation and Adaptive Multi-Granular Tracking
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The impact of negative acknowledgments in shared memory scientific applications
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An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration
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A two-level directory architecture for highly scalable cc-NUMA multiprocessors
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Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
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Modeling the performance of limited pointers directories for cache coherence
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Modeling the performance of limited pointers directories for cache coherence
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The case for simple, visible cache coherency
inferred← citeshttps://doi.org/10.1145/139669.140403openalex-snapshot
The impact of communication locality on large-scale multiprocessor performance
inferred← citeshttps://doi.org/10.1145/143365.143540openalex-snapshot
Closing the window of vulnerability in multiphase memory transactions
inferred← citeshttps://doi.org/10.1145/143371.143540openalex-snapshot
Closing the window of vulnerability in multiphase memory transactions
inferred← citeshttps://doi.org/10.1145/146628.140403openalex-snapshot
The impact of communication locality on large-scale multiprocessor performance
inferred← citeshttps://doi.org/10.1145/152864.152869openalex-snapshot
Waiting algorithms for synchronization in large-scale multiprocessors
inferred← citeshttps://doi.org/10.1145/155332.155338openalex-snapshot
Integrating message-passing and shared-memory
inferred← citeshttps://doi.org/10.1145/155332.155356openalex-snapshot
The shared regions approach to software cache coherence on multiprocessors
inferred← citeshttps://doi.org/10.1145/156668.156705openalex-snapshot
Integrating message-passing and shared-memory
inferred← citeshttps://doi.org/10.1145/158439.158907openalex-snapshot
Cache coherence in large-scale shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1145/165123.165146openalex-snapshot
Adaptive cache coherency for detecting migratory shared data
inferred← citeshttps://doi.org/10.1145/165123.165151openalex-snapshot
Mechanisms for cooperative shared memory
inferred← citeshttps://doi.org/10.1145/165939.165970openalex-snapshot
Anatomy of a message in the Alewife multiprocessor
inferred← citeshttps://doi.org/10.1145/166955.166979openalex-snapshot
The Wisconsin Wind Tunnel: virtual prototyping of parallel computers
inferred← citeshttps://doi.org/10.1145/173284.155338openalex-snapshot
Integrating message-passing and shared-memory
inferred← citeshttps://doi.org/10.1145/173284.155356openalex-snapshot
The shared regions approach to software cache coherence on multiprocessors
inferred← citeshttps://doi.org/10.1145/173682.165146openalex-snapshot
Adaptive cache coherency for detecting migratory shared data
inferred← citeshttps://doi.org/10.1145/173682.165151openalex-snapshot
Mechanisms for cooperative shared memory
inferred← citeshttps://doi.org/10.1145/181181.181271openalex-snapshot
An evaluation of directory protocols for medium-scale shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1145/181181.181281openalex-snapshot
An evaluation of a compiler optimization for improving the performance of a coherence directory
inferred← citeshttps://doi.org/10.1145/181181.181543openalex-snapshot
Performance evaluation of hybrid hardware and software distributed shared memory protocols
inferred← citeshttps://doi.org/10.1145/191995.192021openalex-snapshot
Software versus hardware shared-memory implementation: a case study
inferred← citeshttps://doi.org/10.1145/191995.192027openalex-snapshot
Impact of sharing-based thread placement on multithreaded architectures
inferred← citeshttps://doi.org/10.1145/191995.192060openalex-snapshot
Software-extended coherent shared memory: performance and cost
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