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Distributed-directory scheme: Stanford distributed-directory protocol

https://doi.org/10.1109/2.55504
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/71.80120openalex-snapshot
The performance of spin lock alternatives for shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/17356.17405openalex-snapshot
Multiprocessor cache synchronization: issues, innovations, evolution
inferredcites →https://doi.org/10.1145/17356.17406openalex-snapshot
Memory access buffering in multiprocessors
inferredcites →https://doi.org/10.1145/68182.68188openalex-snapshot
Efficient synchronization primitives for large-scale cache-coherent multiprocessors
inferredcites →https://doi.org/10.1145/70082.68188openalex-snapshot
Efficient synchronization primitives for large-scale cache-coherent multiprocessors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/047134608x.w1661openalex-snapshot
Cache Memory Protocols
inferred← citeshttps://doi.org/10.1002/9781118790229.biblioopenalex-snapshot
Bibliography
inferred← citeshttps://doi.org/10.1007/3-540-44520-x_77openalex-snapshot
Adaptive Proxies: Handling Widely-Shared Data in Shared-Memory Multiprocessors
inferred← citeshttps://doi.org/10.1007/3-540-53065-7_136openalex-snapshot
Scalable cache coherence for large shared memory multiprocessors
inferred← citeshttps://doi.org/10.1007/3-540-55179-4_9openalex-snapshot
A top down approach to the formal specification of SCI cache coherence
inferred← citeshttps://doi.org/10.1007/3-540-55437-8_67openalex-snapshot
Scalable cache coherence for shared memory multiprocessors
inferred← citeshttps://doi.org/10.1007/978-1-4615-3604-8_12openalex-snapshot
The SCI Cache Coherence Protocol
inferred← citeshttps://doi.org/10.1007/978-1-4615-3604-8_8openalex-snapshot
Scalable Cache Coherence Analysis for Shared Memory Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-1-4615-5611-4_26openalex-snapshot
Stable Performance for CC-NUMA Using First-Touch Page Placement and Reactive Proxies
inferred← citeshttps://doi.org/10.1007/978-3-319-30695-7_8openalex-snapshot
Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence
inferred← citeshttps://doi.org/10.1007/978-3-540-30102-8_45openalex-snapshot
A Scalable and Adaptive Directory Scheme for Hardware Distributed Shared Memory
inferred← citeshttps://doi.org/10.1007/bfb0020472openalex-snapshot
Verifying distributed directory-based cache coherence protocols: S3.mp, a case study
inferred← citeshttps://doi.org/10.1007/bfb0057968openalex-snapshot
Reactive proxies: A flexible protocol extension to reduce ccNUMA node controller contention
inferred← citeshttps://doi.org/10.1007/s11227-015-1596-4openalex-snapshot
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study
inferred← citeshttps://doi.org/10.1016/0166-5316(96)00011-9openalex-snapshot
Modelling and validation of shared memory coherency protocols
inferred← citeshttps://doi.org/10.1016/0167-739x(95)00024-mopenalex-snapshot
An argument for simple COMA
inferred← citeshttps://doi.org/10.1016/0743-7315(92)90049-sopenalex-snapshot
Hiding shared memory reference latency on the Galactica Net distributed shared memory architecture
inferred← citeshttps://doi.org/10.1016/b978-1-55860-315-8.50017-8openalex-snapshot
References
inferred← citeshttps://doi.org/10.1016/s0065-2458(03)59005-2openalex-snapshot
Coherence Protocols for Bus-Based and Scalable Multiprocessors, Internet, and Wireless Distributed Computing Environments: A Survey
inferred← citeshttps://doi.org/10.1109/12.755001openalex-snapshot
An efficient tree cache coherence protocol for distributed shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/40.331392openalex-snapshot
Hardware approaches to cache coherence in shared-memory multiprocessors. 2
inferred← citeshttps://doi.org/10.1109/ftpds.1994.494473openalex-snapshot
Redundant linked list based cache coherence protocol
inferred← citeshttps://doi.org/10.1109/hicss.1993.270604openalex-snapshot
A survey of hardware solutions for maintenance of cache coherence in shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/hicss.1994.323134openalex-snapshot
Interleaved dual tag directory scheme for cache coherence
inferred← citeshttps://doi.org/10.1109/hicss.1995.375386openalex-snapshot
A survey of software solutions for maintenance of cache consistency in shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/hpca.1995.386535openalex-snapshot
An argument for simple COMA
inferred← citeshttps://doi.org/10.1109/hpca.1999.744339openalex-snapshot
Lightweight hardware distributed shared memory supported by generalized combining
inferred← citeshttps://doi.org/10.1109/icpp.1993.14openalex-snapshot
A Chained-Directory Cache Choerence Protocol for Multiprocessors
inferred← citeshttps://doi.org/10.1109/ipps.1991.153798openalex-snapshot
A linked list cache coherence protocol: verifying the bottom layer
inferred← citeshttps://doi.org/10.1109/ispan.1996.509027openalex-snapshot
A new cache directory scheme
inferred← citeshttps://doi.org/10.1109/jec-ecc.2013.6766389openalex-snapshot
Hybrid limited-pointer linked-list cache directory and cache coherence protocol
inferred← citeshttps://doi.org/10.1109/pccc.1996.493628openalex-snapshot
The JUMP-1 router chip: a versatile router for supporting a distributed shared memory
inferred← citeshttps://doi.org/10.1109/tencon.1993.319969openalex-snapshot
A heterogeneous multiprocessing computer system with shared memory
inferred← citeshttps://doi.org/10.1109/trustcom.2013.250openalex-snapshot
Performance Evaluation of the Time Analysable On-Demand Coherent Cache
inferred← citeshttps://doi.org/10.1117/12.192215openalex-snapshot
Local-Area MultiProcessor: the scalable coherent interface
inferred← citeshttps://doi.org/10.1145/115952.115983openalex-snapshot
Modeling the performance of limited pointers directories for cache coherence
inferred← citeshttps://doi.org/10.1145/115953.115983openalex-snapshot
Modeling the performance of limited pointers directories for cache coherence
inferred← citeshttps://doi.org/10.1145/379189.379198openalex-snapshot
Two economical directory schemes for large-scale cache coherent multiprocessors
inferred← citeshttps://doi.org/10.2991/iccse-15.2015.52openalex-snapshot
Cache Coherence Protocols in Shared-Memory Multiprocessors
inferred← citeshttps://doi.org/10.5555/1089053.1089104openalex-snapshot
Synchronization and cache coherence in computer design
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