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Lisp on a reduced-instruction-set processor: characterization and optimization
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.67openalex-snapshot
Lisp on a reduced-instruction-set processor: characterization and optimization
inferredcites →https://doi.org/10.1109/isscc.1987.1157084openalex-snapshot
A 553K-transistor LISP processor chip
inferredcites →https://doi.org/10.1109/jssc.1987.1052817openalex-snapshot
A 553 K-transistor LISP processor chip
inferredcites →https://doi.org/10.1109/ms.1987.231067openalex-snapshot
Implementing and Optimizing Lisp for the Cray
inferredcites →https://doi.org/10.1145/12276.13333openalex-snapshot
ORBIT: an optimizing compiler for scheme
inferredcites →https://doi.org/10.1145/12276.13338openalex-snapshot
Global register allocation at link time
inferredcites →https://doi.org/10.1145/2465.214917openalex-snapshot
Reduced instruction set computers
inferredcites →https://doi.org/10.1145/30350.30384openalex-snapshot
Architectural tradeoffs in the design of MIPS-X
inferredcites →https://doi.org/10.1145/319838.319862openalex-snapshot
LISP on a reduced-instruction-set-processor
inferredcites →https://doi.org/10.1145/36177.36183openalex-snapshot
Tags and type checking in LISP: hardware and software approaches
inferredcites →https://doi.org/10.1145/800230.807000openalex-snapshot
An optimizing compiler for lexically scoped LISP
inferredcites →https://doi.org/10.1145/800230.807001openalex-snapshot
Current status of a portable LISP compiler
inferredcites →https://doi.org/10.1145/989393.989415openalex-snapshot
Global register allocation at link time
inferredcites →https://doi.org/10.7551/mitpress/5298.001.0001openalex-snapshot
Performance and Evaluation of LISP Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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The Scalable Processor Architecture (SPARC)
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SPARC: Scalable Processor Architecture
inferred← citeshttps://doi.org/10.1007/978-1-4615-3752-6_5openalex-snapshot
COLIBRI: A Coprocessor for LISP based on RISC
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Scoping the Window to the Universe; Design Considerations and Expert Evaluation of an Augmented Reality Mobile Application for Astronomy Education
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Architectural Features of Computer Systems for Autonomous Mobile Robot Applications
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Measuring the cost of storage management
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Sequential architecture models for Prolog: A performance comparison
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Interprocedural analysis vs. procedure integration
inferred← citeshttps://doi.org/10.1016/0165-6074(89)90027-6openalex-snapshot
Inter: An inexpensive inter-procedural register allocator
inferred← citeshttps://doi.org/10.1016/0952-1976(90)90018-hopenalex-snapshot
MARS: a RISC-based architecture for Lisp
inferred← citeshttps://doi.org/10.1109/12.324558openalex-snapshot
A parallel virtual machine for programs composed of abstract data types
inferred← citeshttps://doi.org/10.1109/hpca.1995.386560openalex-snapshot
The Named-State Register File: implementation and performance
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The Impact Of Code Density On Instruction Cache Performance
inferred← citeshttps://doi.org/10.1109/mc.1987.1663696openalex-snapshot
And Now a Case for More Complex Instruction Sets
inferred← citeshttps://doi.org/10.1109/tai.1989.65321openalex-snapshot
MARS-a RISC-based architecture for LISP
inferred← citeshttps://doi.org/10.1109/tai.1989.65323openalex-snapshot
Current and future trends in artificial intelligence architectures and programming languages
inferred← citeshttps://doi.org/10.1109/vtsa.1989.68647openalex-snapshot
MARS-Multiprocessor architecture reconciling symbolic with numerical processing-a CPU ensemble with zero-delay branch/jump
inferred← citeshttps://doi.org/10.1145/103727.103730openalex-snapshot
Architectural support for reduced register saving/restoring in single-window register files
inferred← citeshttps://doi.org/10.1145/113445.113452openalex-snapshot
Procedure merging with instruction caches
inferred← citeshttps://doi.org/10.1145/129393.129395openalex-snapshot
Experience with a software-defined machine architecture
inferred← citeshttps://doi.org/10.1145/1317258.1317260openalex-snapshot
A study of LISP on a multiprocessor preliminary version
inferred← citeshttps://doi.org/10.1145/292469.292471openalex-snapshot
Garbage collecting the Internet
inferred← citeshttps://doi.org/10.1145/30350.30384openalex-snapshot
Architectural tradeoffs in the design of MIPS-X
inferred← citeshttps://doi.org/10.1145/36177.36183openalex-snapshot
Tags and type checking in LISP: hardware and software approaches
inferred← citeshttps://doi.org/10.1145/59287.59289openalex-snapshot
A simple interprocedural register allocation algorithm and its effectiveness for LISP
inferred← citeshttps://doi.org/10.1145/68182.68196openalex-snapshot
Data buffering: run-time versus compile-time support
inferred← citeshttps://doi.org/10.1145/74877.74882openalex-snapshot
Design of the opportunistic garbage collector
inferred← citeshttps://doi.org/10.1145/74925.74954openalex-snapshot
The impact of code density on instruction cache performance
inferred← citeshttps://doi.org/10.1145/91556.91595openalex-snapshot
Trap architectures for Lisp systems
inferred← citeshttps://doi.org/10.1145/93542.93551openalex-snapshot
Register allocation across procedure and module boundaries
inferred← citeshttps://doi.org/10.1145/960116.53999openalex-snapshot
Minimizing register usage penalty at procedure calls
inferred← citeshttps://doi.org/10.1145/989393.989422openalex-snapshot
Register windows vs. register allocation
inferred← citeshttps://doi.org/10.1184/r1/6604622openalex-snapshot
Data-flow analysis and type recovery in Scheme
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