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Internet Streaming SIMD Extensions
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/40.526924openalex-snapshot
MMX technology extension to the Intel architecture
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11403937_42openalex-snapshot
Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study
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Efficient SIMD Numerical Interpolation
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Automatic Detection of Saturation and Clipping Idioms
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FPGA Resource Reduction Through Truncated Multiplication
inferred← citeshttps://doi.org/10.1007/3-540-45706-2_120openalex-snapshot
Performance Scalability of Multimedia Instruction Set Extensions
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High-Bandwidth Address Generation Unit
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Optimizing 3D Convolutions for Wavelet Transforms on CPUs with SSE Units and GPUs
inferred← citeshttps://doi.org/10.1007/978-3-7908-1810-9_11openalex-snapshot
Parallel Implementations of Self-Organizing Maps
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Efficient evaluation methods of elementary functions suitable for SIMD computation
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Avoiding Conversion and Rearrangement Overhead in SIMD Architectures
inferred← citeshttps://doi.org/10.1007/s11227-012-0790-xopenalex-snapshot
Algorithms and architectures for 2D discrete wavelet transform
inferred← citeshttps://doi.org/10.1007/s11227-012-0803-9openalex-snapshot
Development of a unified FDTD-FEM library for electromagnetic analysis with CPU and GPU computing
inferred← citeshttps://doi.org/10.1007/s11227-013-1065-xopenalex-snapshot
Performance analysis of SSE and AVX instructions in multi-core CPUs and GPU computing on FDTD scheme for solid and fluid vibration problems
inferred← citeshttps://doi.org/10.1007/s11265-005-6651-6openalex-snapshot
Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions
inferred← citeshttps://doi.org/10.1007/s11265-007-0126-xopenalex-snapshot
Configurable Data Memory for Multimedia Processing
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High-bandwidth Address Generation Unit
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Coherent Photon Mapping on the Intel MIC Architecture
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Practical Performance Evaluation of Space Optimal Erasure Codes for High-Speed Data Storage Systems
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Efficient fuzzy compiler for SIMD architectures
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High performance SIMD marching cubes isosurface extraction on commodity computers
inferred← citeshttps://doi.org/10.1016/j.cpc.2012.09.025openalex-snapshot
Performance analysis of the FDTD method applied to holographic volume gratings: Multi-core CPU versus GPU computing
inferred← citeshttps://doi.org/10.1016/j.cpc.2015.01.017openalex-snapshot
Multi-GPU and multi-CPU accelerated FDTD scheme for vibroacoustic applications
inferred← citeshttps://doi.org/10.1016/j.image.2014.10.003openalex-snapshot
A parallel H.264/SVC encoder for high definition video conferencing
inferred← citeshttps://doi.org/10.1016/j.micpro.2004.10.002openalex-snapshot
Multimedia extensions for general purpose microprocessors: a survey
inferred← citeshttps://doi.org/10.1016/j.sysarc.2003.06.003openalex-snapshot
Implementation of a streaming execution unit
inferred← citeshttps://doi.org/10.1016/s0141-9331(03)00062-0openalex-snapshot
On the suitability of SIMD extensions for neural network simulation
inferred← citeshttps://doi.org/10.1093/comjnl/bxm099openalex-snapshot
A Review of SIMD Multimedia Extensions and their Usage in Scientific and Engineering Applications
inferred← citeshttps://doi.org/10.1109/30.883435openalex-snapshot
Performance of an advanced video codec on a general-purpose processor with media ISA extensions
inferred← citeshttps://doi.org/10.1109/40.865866openalex-snapshot
Implementing streaming SIMD extensions on the Pentium III processor
inferred← citeshttps://doi.org/10.1109/acssc.2000.911211openalex-snapshot
Variable-correction truncated floating point multipliers
inferred← citeshttps://doi.org/10.1109/apasic.2000.896985openalex-snapshot
3D graphics system with VLIW processor for geometry acceleration
inferred← citeshttps://doi.org/10.1109/aps.2012.6348986openalex-snapshot
Double precision performance of streaming SIMD extensions instructions for the FDTD computation
inferred← citeshttps://doi.org/10.1109/ares.2013.23openalex-snapshot
ARMORED: CPU-Bound Encryption for Android-Driven ARM Devices
inferred← citeshttps://doi.org/10.1109/arith.2005.45openalex-snapshot
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
inferred← citeshttps://doi.org/10.1109/asap.2000.862389openalex-snapshot
A vector multiprocessor for real-time multi-user detection in spread-spectrum communication
inferred← citeshttps://doi.org/10.1109/camp.2000.875984openalex-snapshot
Multi-media extensions in super-pipelined micro-architectures. A new case for SIMD processing?
inferred← citeshttps://doi.org/10.1109/coolchips68842.2026.11556515openalex-snapshot
RX VPU: A High-Efficiency Variable-Length Vector Architecture with Widening Reduction MAC for Embedded CNNs
inferred← citeshttps://doi.org/10.1109/dftvs.2003.1250146openalex-snapshot
An efficient functional test for the massively-parallel C·RAM logic-enhanced memory architecture
inferred← citeshttps://doi.org/10.1109/dsd.2002.1115364openalex-snapshot
Implementation of a streaming execution unit
inferred← citeshttps://doi.org/10.1109/dsd.2009.189openalex-snapshot
SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform
inferred← citeshttps://doi.org/10.1109/empdp.2003.1183565openalex-snapshot
Reducing 3D wavelet transform execution time through the Streaming SIMD Extensions
inferred← citeshttps://doi.org/10.1109/eurmic.2000.874659openalex-snapshot
Complex streamed instructions: introduction and initial evaluation
inferred← citeshttps://doi.org/10.1109/hnicem.2014.7016212openalex-snapshot
Beyond multi-core: A survey of architectural innovations on microprocessor
inferred← citeshttps://doi.org/10.1109/icassp.2004.1327094openalex-snapshot
Fast implementation of the MPEG-4 AAC main and low complexity decoder
inferred← citeshttps://doi.org/10.1109/iccd.2001.955074openalex-snapshot
Combined IEEE compliant and truncated floating point multipliers for reduced power dissipation
inferred← citeshttps://doi.org/10.1109/icce.2000.854655openalex-snapshot
Performance of an advanced video codec on a general-purpose processor with media ISA extensions
inferred← citeshttps://doi.org/10.1109/icdcs57875.2023.00059openalex-snapshot
CAUSEC: Cache-Based Secure Key Computation with (Mostly) Deprivileged Execution
inferred← citeshttps://doi.org/10.1109/icpads.2005.145openalex-snapshot
Efficient Polynomial Root Finding Using SIMD Extensions
inferred← citeshttps://doi.org/10.1109/iiswc.2017.8167776openalex-snapshot
Characterizing diverse handheld apps for customized hardware acceleration
inferred← citeshttps://doi.org/10.1109/ipdps.2003.1213152openalex-snapshot
Vectorization of multigrid codes using SIMD ISA extensions
inferred← citeshttps://doi.org/10.1109/ipdps.2012.102openalex-snapshot
Radio Astronomy Beam Forming on Many-Core Architectures
inferred← citeshttps://doi.org/10.1109/ispass.2005.1430571openalex-snapshot
On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications
inferred← citeshttps://doi.org/10.1109/ispass.2007.363737openalex-snapshot
Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications
inferred← citeshttps://doi.org/10.1109/iwsoc.2006.348239openalex-snapshot
A Distributed and Shared Register File for a Multiprocessor-on-Chip to Support Real-Time Applications
inferred← citeshttps://doi.org/10.1109/map.2012.6293973openalex-snapshot
Performance of Streaming SIMD Extensions Instructions for the FDTD Computation
inferred← citeshttps://doi.org/10.1109/micro.2018.00075openalex-snapshot
CritICs Critiquing Criticality in Mobile Apps
inferred← citeshttps://doi.org/10.1109/pacrim.2001.953568openalex-snapshot
Performance evaluation of a vector architecture for multiuser detection in CDMA communications
inferred← citeshttps://doi.org/10.1109/pact.2000.888333openalex-snapshot
Exploring the limits of sub-word level parallelism
inferred← citeshttps://doi.org/10.1109/pact.2001.953289openalex-snapshot
Implementation and evaluation of the Complex Streamed Instruction set
inferred← citeshttps://doi.org/10.1109/pact.2003.1238010openalex-snapshot
Compilation, architectural support, and evaluation of SIMD graphics pipeline programs on a general-purpose CPU
inferred← citeshttps://doi.org/10.1109/rt.2006.280230openalex-snapshot
Design for Parallel Interactive Ray Tracing Systems
inferred← citeshttps://doi.org/10.1109/sc.2004.69openalex-snapshot
Analysis and Performance Results of a Molecular Modeling Application on Merrimac
inferred← citeshttps://doi.org/10.1109/tc.2002.1047756openalex-snapshot
Measuring the performance of multimedia instruction sets
inferred← citeshttps://doi.org/10.1109/tc.2003.1223637openalex-snapshot
Bottlenecks in multimedia processing with SIMD style extensions and architectural enhancements
inferred← citeshttps://doi.org/10.1109/tcad.2025.3649448openalex-snapshot
An Arbitrary Register Grouping Scheme for RISC-V Vector Extension: Compilation Support and Hardware Implementation
inferred← citeshttps://doi.org/10.1109/tcsvt.2002.800865openalex-snapshot
Overview of research efforts on media ISA extensions and their usage in video coding
inferred← citeshttps://doi.org/10.1109/tcsvt.2002.800866openalex-snapshot
A survey of media processing approaches
inferred← citeshttps://doi.org/10.1109/tcsvt.2004.835148openalex-snapshot
Byte and Modulo Addressable Parallel Memory Architecture for Video Coding
inferred← citeshttps://doi.org/10.1109/tcsvt.2014.2364413openalex-snapshot
SIMD Acceleration for HEVC Decoding
inferred← citeshttps://doi.org/10.1109/tvlsi.2004.840415openalex-snapshot
The CSI multimedia architecture
inferred← citeshttps://doi.org/10.1111/j.1467-8659.2010.01844.xopenalex-snapshot
Review: Kd‐tree Traversal Algorithms for Ray Tracing
inferred← citeshttps://doi.org/10.1111/j.1467-8659.2012.03073.xopenalex-snapshot
Improving Data Locality for Efficient In‐Core Path Tracing
inferred← citeshttps://doi.org/10.1117/12.896873openalex-snapshot
Analysis of the diffraction efficiency of reflection and transmission holographic gratings by means of a parallel FDTD approach
inferred← citeshttps://doi.org/10.1145/1062261.1062277openalex-snapshot
Reconfigurable universal SAD-multiplier array
inferred← citeshttps://doi.org/10.1145/1084834.1084909openalex-snapshot
Improving superword level parallelism support in modern compilers
inferred← citeshttps://doi.org/10.1145/1168857.1168903openalex-snapshot
Tradeoffs in transactional memory virtualization
inferred← citeshttps://doi.org/10.1145/1168917.1168903openalex-snapshot
Tradeoffs in transactional memory virtualization
inferred← citeshttps://doi.org/10.1145/1168918.1168903openalex-snapshot
Tradeoffs in transactional memory virtualization
inferred← citeshttps://doi.org/10.1145/1168919.1168903openalex-snapshot
Tradeoffs in transactional memory virtualization
inferred← citeshttps://doi.org/10.1145/1274971.1274991openalex-snapshot
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
inferred← citeshttps://doi.org/10.1145/1531743.1531753openalex-snapshot
A multi-streaming SIMD architecture for multimedia applications
inferred← citeshttps://doi.org/10.1145/1534916.1534922openalex-snapshot
Vector Processing as a Soft Processor Accelerator
inferred← citeshttps://doi.org/10.1145/1538917.1538918openalex-snapshot
Mostly static program partitioning of binary executables
inferred← citeshttps://doi.org/10.1145/2903150.2903485openalex-snapshot
Towards low-power embedded vector processor
inferred← citeshttps://doi.org/10.1145/3075618openalex-snapshot
An Integrated Vector-Scalar Design on an In-Order ARM Core
inferred← citeshttps://doi.org/10.1145/3514246openalex-snapshot
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework
inferred← citeshttps://doi.org/10.1145/3620665.3640401openalex-snapshot
A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors
inferred← citeshttps://doi.org/10.1145/3735452.3735527openalex-snapshot
DSP-MLIR: A Domain-Specific Language and MLIR Dialect for Digital Signal Processing
inferred← citeshttps://doi.org/10.1155/2019/8908950openalex-snapshot
Effective Parallelization Method for Object Recognition in 2D Sonar Images Based on Task Partitioning
inferred← citeshttps://doi.org/10.1190/segam2012-0890.1openalex-snapshot
Pyramid-shaped grid for elastic wave propagation
inferred← citeshttps://doi.org/10.1201/9780203908068-10openalex-snapshot
Digital Signal Processing on MMX Technology
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Software Design for Petascale Climate Science
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Parallelization of the K-Means++ Clustering Algorithm
inferred← citeshttps://doi.org/10.20868/upm.thesis.809openalex-snapshot
Modelo de controlador borroso completamente programable de altas prestaciones y su desarrollo
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Network-Integrated Multimedia Middleware, Services, and Applications
inferred← citeshttps://doi.org/10.2514/1.i010916openalex-snapshot
On-Board Decision Making in Space with Deep Neural Networks and RISC-V Vector Processors
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Extending the NOEL-V Platform with a RISC-V Vector Processor for Space Applications
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A metadata-enhanced framework for high performance visual effects
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Fast Overlap Detection between Hard-Core Colloidal Cuboids and Spheres. The OCSI Algorithm
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High-performance elliptic curve cryptography
inferred← citeshttps://doi.org/10.5753/ctd.2023.230156openalex-snapshot
High-Performance Elliptic Curve Cryptography: A SIMD Approach to Modern Curves
inferred← citeshttps://doi.org/10.5753/jbcs.2026.5548openalex-snapshot
High-Performance Elliptic Curve Cryptography: A SIMD Approach to Modern Curves (Thesis Distillation)
inferred← citeshttps://doi.org/10.5753/sbseg_estendido.2024.241959openalex-snapshot
High-Performance Elliptic Curve Cryptography: A SIMD Approach to Modern Curves
inferred← citeshttps://doi.org/10.5821/dissertation-2117-107712openalex-snapshot
Design of energy-efficient vector units for in-order cores
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Parallel video decoding
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Specialization and reconfiguration of lightweight mobile processors for data-parallel applications
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Scalable block processing algorithms
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High-speed cryptography and cryptanalysis
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