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An interconnect-centric design flow for nanometer technologies
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4757-2363-2openalex-snapshot
On Optimal Interconnections for VLSI
inferredcites →https://doi.org/10.1007/978-1-4757-3748-6_3openalex-snapshot
Multilevel Hypergraph Partitioning
inferredcites →https://doi.org/10.1016/s0167-9260(87)80003-2openalex-snapshot
A global router based on a multicommodity flow model
inferredcites →https://doi.org/10.1016/s0167-9260(96)00008-9openalex-snapshot
Performance optimization of VLSI interconnect layout
inferredcites →https://doi.org/10.1090/s0025-5718-1977-0431719-xopenalex-snapshot
Multi-Level Adaptive Solutions to Boundary-Value Problems
inferredcites →https://doi.org/10.1109/43.137519openalex-snapshot
Provably good performance-driven global routing
inferredcites →https://doi.org/10.1109/43.365123openalex-snapshot
Optimal wiresizing under Elmore delay model
inferredcites →https://doi.org/10.1109/43.673630openalex-snapshot
Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design
inferredcites →https://doi.org/10.1109/43.703830openalex-snapshot
Optimal clock period clustering for sequential circuits with retiming
inferredcites →https://doi.org/10.1109/43.752925openalex-snapshot
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing
inferredcites →https://doi.org/10.1109/43.766728openalex-snapshot
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
inferredcites →https://doi.org/10.1109/43.784121openalex-snapshot
An efficient and optimal algorithm for simultaneous buffer and wire sizing
inferredcites →https://doi.org/10.1109/43.828553openalex-snapshot
A global wiring paradigm for deep submicron design
inferredcites →https://doi.org/10.1109/43.97624openalex-snapshot
FastCap: a multipole accelerated 3-D capacitance extraction program
inferredcites →https://doi.org/10.1109/92.335010openalex-snapshot
Simultaneous driver and wire sizing for performance and power optimization
inferredcites →https://doi.org/10.1109/92.748202openalex-snapshot
Multilevel hypergraph partitioning: applications in VLSI domain
inferredcites →https://doi.org/10.1109/aspdac.1999.759720openalex-snapshot
Interconnect delay estimation models for synthesis and design planning
inferredcites →https://doi.org/10.1109/aspdac.2000.835138openalex-snapshot
Edge separability based circuit clustering with application to circuit partitioning
inferredcites →https://doi.org/10.1109/aspdac.2000.835140openalex-snapshot
Performance driven multiway partitioning
inferredcites →https://doi.org/10.1109/dac.1988.14840openalex-snapshot
An interactive maze router with hints
inferredcites →https://doi.org/10.1109/dac.1990.114929openalex-snapshot
A gridless router for industrial design rules
inferredcites →https://doi.org/10.1109/dac.1995.250053openalex-snapshot
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
inferredcites →https://doi.org/10.1109/dac.1996.545608openalex-snapshot
New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
inferredcites →https://doi.org/10.1109/dac.1996.545610openalex-snapshot
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
inferredcites →https://doi.org/10.1109/dac.1997.597203openalex-snapshot
Multilevel Hypergraph Partitioning: Application In Vlsi Domain
inferredcites →https://doi.org/10.1109/dac.1997.597217openalex-snapshot
Optimal Wire-sizing Function With Fringing Capacitance Consideration
inferredcites →https://doi.org/10.1109/dac.1999.781360openalex-snapshot
Simultaneous circuit partitioning/clustering with retiming for performance optimization
inferredcites →https://doi.org/10.1109/dac.1999.781368openalex-snapshot
Interconnect estimation and planning for deep submicron designs
inferredcites →https://doi.org/10.1109/edtc.1997.582366openalex-snapshot
Shaping a VLSI wire to minimize Elmore delay
inferredcites →https://doi.org/10.1109/eurdac.1995.528550openalex-snapshot
Post routing performance optimization via tapered link insertion and wiresizing
inferredcites →https://doi.org/10.1109/iccad.1988.122488openalex-snapshot
A new algorithm for standard cell global routing
inferredcites →https://doi.org/10.1109/iccad.1993.580152openalex-snapshot
Optimal wiresizing under the distributed Elmore delay model
inferredcites →https://doi.org/10.1109/iccad.1994.629837openalex-snapshot
Rc Interconnect Synthesis-a Moment Fitting Approach
inferredcites →https://doi.org/10.1109/iccad.1995.480004openalex-snapshot
Optimal wire sizing and buffer insertion for low power and a generalized delay model
inferredcites →https://doi.org/10.1109/iccad.1995.480005openalex-snapshot
A sequential quadratic programming approach to concurrent gate and wire sizing
inferredcites →https://doi.org/10.1109/iccad.1995.480173openalex-snapshot
Optimal wiresizing for interconnects with multiple sources
inferredcites →https://doi.org/10.1109/iccad.1996.568937openalex-snapshot
Optimal non-uniform wire-sizing under the Elmore delay model
inferredcites →https://doi.org/10.1109/iccad.1996.568938openalex-snapshot
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
inferredcites →https://doi.org/10.1109/iccad.1996.569580openalex-snapshot
An efficient approach to simultaneous transistor and interconnect sizing
inferredcites →https://doi.org/10.1109/iccad.1997.643604openalex-snapshot
Global interconnect sizing and spacing with consideration of coupling capacitance
inferredcites →https://doi.org/10.1109/iccad.1997.643617openalex-snapshot
Interconnect layout optimization under higher-order RLC model
inferredcites →https://doi.org/10.1109/iccad.1999.810642openalex-snapshot
An implicit connection graph maze routing algorithm for ECO routing
inferredcites →https://doi.org/10.1109/iccad.1999.810675openalex-snapshot
Buffer block planning for interconnect-driven floorplanning
inferredcites →https://doi.org/10.1109/iccad.1999.810689openalex-snapshot
Is wire tapering worthwhile?
inferredcites →https://doi.org/10.1109/iccad.2000.896441openalex-snapshot
Physical planning with retiming
inferredcites →https://doi.org/10.1109/iccad.2000.896469openalex-snapshot
Multilevel optimization for large-scale circuit placement
inferredcites →https://doi.org/10.1109/iscas.1990.112223openalex-snapshot
Buffer placement in distributed RC-tree networks for minimal Elmore delay
inferredcites →https://doi.org/10.1109/iscas.1994.408838openalex-snapshot
Dynamically-wiresized Elmore-based routing constructions
inferredcites →https://doi.org/10.1109/iscas.1995.521486openalex-snapshot
Performance driven routing with multiple sources
inferredcites →https://doi.org/10.1109/jproc.1998.658762openalex-snapshot
Cramming More Components Onto Integrated Circuits
inferredcites →https://doi.org/10.1109/lpe.1996.547521openalex-snapshot
Simultaneous buffer and wire sizing for performance and power optimization
inferredcites →https://doi.org/10.1109/mcmc.1996.510780openalex-snapshot
A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies
inferredcites →https://doi.org/10.1109/tcad.1984.1270061openalex-snapshot
Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools
inferredcites →https://doi.org/10.1145/123186.123422openalex-snapshot
A gridless router for industrial design rules
inferredcites →https://doi.org/10.1145/157485.164662openalex-snapshot
High-performance routing trees with identified critical sinks
inferredcites →https://doi.org/10.1145/157485.165065openalex-snapshot
Performance-driven interconnect design based on distributed RC delay model
inferredcites →https://doi.org/10.1145/217474.217612openalex-snapshot
Simultaneous gate and interconnect sizing for circuit-level delay optimization
inferredcites →https://doi.org/10.1145/240518.240594openalex-snapshot
New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
inferredcites →https://doi.org/10.1145/240518.240596openalex-snapshot
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
inferredcites →https://doi.org/10.1145/266021.266273openalex-snapshot
Multilevel hypergraph partitioning
inferredcites →https://doi.org/10.1145/266021.266295openalex-snapshot
Optimal wire-sizing function with fringing capacitance consideration
inferredcites →https://doi.org/10.1145/266021.266303openalex-snapshot
Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology
inferredcites →https://doi.org/10.1145/267665.267689openalex-snapshot
Performance driven global routing for standard cell design
inferredcites →https://doi.org/10.1145/274535.274566openalex-snapshot
Analysis, reduction and avoidance of crosstalk on VLSI chips
inferredcites →https://doi.org/10.1145/277044.277144openalex-snapshot
Performance driven multi-layer general area routing for PCB/MCM designs
inferredcites →https://doi.org/10.1145/288548.289079openalex-snapshot
Multiway partitioning with pairwise movement
inferredcites →https://doi.org/10.1145/299996.300041openalex-snapshot
Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model
inferredcites →https://doi.org/10.1145/309847.309980openalex-snapshot
Simultaneous circuit partitioning/clustering with retiming for performance optimization
inferredcites →https://doi.org/10.1145/309847.309988openalex-snapshot
Interconnect estimation and planning for deep submicron designs
inferredcites →https://doi.org/10.1145/332357.332372openalex-snapshot
Pseudo pin assignment with crosstalk noise control
inferredcites →https://doi.org/10.1145/332357.332398openalex-snapshot
Routability-driven repeater block planning for interconnect-centric floorplanning
inferredcites →https://doi.org/10.1145/368434.368728openalex-snapshot
Edge separability based circuit clustering with application to circuit partitioning
inferredcites →https://doi.org/10.1145/368434.368736openalex-snapshot
Performance driven multiway partitioning
inferredcites →https://doi.org/10.1155/1997/73654openalex-snapshot
Combining Technology Mapping With Layout
inferredcites →https://doi.org/10.5555/1711932.1711941openalex-snapshot
A global router based on a multicommodity flow model
inferredcites →https://doi.org/10.5555/191326.191506openalex-snapshot
RC interconnect synthesis—a moment fitting approach
inferredcites →https://doi.org/10.5555/224270.224291openalex-snapshot
Post routing performance optimization via tapered link insertion and wiresizing
inferredcites →https://doi.org/10.5555/224841.224872openalex-snapshot
Optimal wire sizing and buffer insertion for low power and a generalized delay model
inferredcites →https://doi.org/10.5555/224841.224873openalex-snapshot
A sequential quadratic programming approach to concurrent gate and wire sizing
inferredcites →https://doi.org/10.5555/224841.225116openalex-snapshot
Optimal wiresizing for interconnects with multiple sources
inferredcites →https://doi.org/10.5555/244522.244529openalex-snapshot
Optimal non-uniform wire-sizing under the Elmore delay model
inferredcites →https://doi.org/10.5555/244522.244530openalex-snapshot
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
inferredcites →https://doi.org/10.5555/244522.244552openalex-snapshot
An efficient approach to simultaneous transistor and interconnect sizing
inferredcites →https://doi.org/10.5555/252493.252617openalex-snapshot
Simultaneous buffer and wire sizing for performance and power optimization
inferredcites →https://doi.org/10.5555/259794.259893openalex-snapshot
Optimal wiresizing under the distributed Elmore delay model
inferredcites →https://doi.org/10.5555/266388.266566openalex-snapshot
Global interconnect sizing and spacing with consideration of coupling capacitance
inferredcites →https://doi.org/10.5555/266388.266618openalex-snapshot
Interconnect layout optimization under higher-order RLC model
inferredcites →https://doi.org/10.5555/285730.285845openalex-snapshot
An interactive maze router with hints
inferredcites →https://doi.org/10.5555/339492.339614openalex-snapshot
An implicit connection graph maze routing algorithm for ECO routing
inferredcites →https://doi.org/10.5555/339492.340040openalex-snapshot
Buffer block planning for interconnect-driven floorplanning
inferredcites →https://doi.org/10.5555/602902.602904openalex-snapshot
Physical planning with retiming
inferredcites →https://doi.org/10.5555/602902.602941openalex-snapshot
Multilevel optimization for large-scale circuit placement
inferredcites →https://doi.org/10.5555/787260.787672openalex-snapshot
Shaping a VLSI wire to minimize Elmore delay
inferredcites →https://doi.org/10.7551/mitpress/12274.003.0027openalex-snapshot
Cramming More Components onto Integrated Circuits (1965)
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Hierarchical Methodology Approach to SOC Design - A comprehensive look
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A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation
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A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer
inferred← citeshttps://doi.org/10.1109/lpe.2003.1231838openalex-snapshot
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI
inferred← citeshttps://doi.org/10.1109/lpe.2005.195512openalex-snapshot
Driver pre-emphasis techniques for on-chip global buses
inferred← citeshttps://doi.org/10.1109/mcas.2023.3325498openalex-snapshot
Women in Circuits and Systems (WiCAS) at NEWCAS 2023 [Women in CAS]
inferred← citeshttps://doi.org/10.1109/mcas.2023.3331327openalex-snapshot
An Interview With Professor Jason Cong [Interview]
inferred← citeshttps://doi.org/10.1109/mdat.2025.3603108openalex-snapshot
From Classical Algorithms to AI: Evolving Trends in VLSI Physical Design Automation
inferred← citeshttps://doi.org/10.1109/mwscas.2006.381800openalex-snapshot
Interconnect-Centric High Level Synthesis for Enhanced Layouts with Reduced Wire Length
inferred← citeshttps://doi.org/10.1109/socc.2005.1554499openalex-snapshot
Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs
inferred← citeshttps://doi.org/10.1109/socdc.2008.4815587openalex-snapshot
Design ASNoC for low-power SoCs
inferred← citeshttps://doi.org/10.1109/spi.2002.258279openalex-snapshot
Imperfect Return Path Effects on RLCG Model of Single and Coupled Interconnects: Propagation delay, Rise Time and Crosstalk Prediction
inferred← citeshttps://doi.org/10.1109/tcad.2002.1013890openalex-snapshot
An interconnect energy model considering coupling effects
inferred← citeshttps://doi.org/10.1109/tcad.2003.809661openalex-snapshot
Multilevel global placement with congestion control
inferred← citeshttps://doi.org/10.1109/tcad.2004.825841openalex-snapshot
Repeater Scaling and Its Impact on CAD
inferred← citeshttps://doi.org/10.1109/tcad.2004.825870openalex-snapshot
Optimality and Scalability Study of Existing Placement Algorithms
inferred← citeshttps://doi.org/10.1109/tcad.2004.842820openalex-snapshot
Interconnect-aware low-power high-level synthesis
inferred← citeshttps://doi.org/10.1109/tcad.2005.844088openalex-snapshot
Simultaneous power supply planning and noise avoidance in floorplan design
inferred← citeshttps://doi.org/10.1109/tcad.2005.846369openalex-snapshot
Congestion-aware topology optimization of structured power/ground networks
inferred← citeshttps://doi.org/10.1109/tcad.2005.852672openalex-snapshot
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets
inferred← citeshttps://doi.org/10.1109/tcad.2005.860956openalex-snapshot
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
inferred← citeshttps://doi.org/10.1109/tcad.2006.870071openalex-snapshot
Partition-based algorithm for power grid design using locality
inferred← citeshttps://doi.org/10.1109/tcad.2006.884861openalex-snapshot
Performance-Driven Crosstalk Elimination at Postcompiler Level—The Case of Low-Crosstalk Op-Code Assignment
inferred← citeshttps://doi.org/10.1109/tcad.2008.2006149openalex-snapshot
Buffering Interconnect for Multicore Processor Designs
inferred← citeshttps://doi.org/10.1109/tcad.2015.2404871openalex-snapshot
Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure
inferred← citeshttps://doi.org/10.1109/tcad.2017.2652221openalex-snapshot
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations
inferred← citeshttps://doi.org/10.1109/tcsi.2008.2010155openalex-snapshot
Serial-Link Bus: A Low-Power On-Chip Bus Architecture
inferred← citeshttps://doi.org/10.1109/ted.2003.812104openalex-snapshot
Optimal global interconnects for GSI
inferred← citeshttps://doi.org/10.1109/ted.2004.829517openalex-snapshot
Analysis and Optimization of Coplanar RLC Lines for GSI Global Interconnection
inferred← citeshttps://doi.org/10.1109/ted.2013.2275259openalex-snapshot
Low-Resistivity Long-Length Horizontal Carbon Nanotube Bundles for Interconnect Applications—Part I: Process Development
inferred← citeshttps://doi.org/10.1109/tie.2010.2081953openalex-snapshot
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network
inferred← citeshttps://doi.org/10.1109/tvlsi.2003.817551openalex-snapshot
Crosstalk noise reduction in synthesized digital logic circuits
inferred← citeshttps://doi.org/10.1109/tvlsi.2004.836294openalex-snapshot
CAD for nanometer silicon design challenges and success
inferred← citeshttps://doi.org/10.1109/tvlsi.2004.836311openalex-snapshot
Interconnect accelerating techniques for sub-100-nm gigascale systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2006.886400openalex-snapshot
Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization
inferred← citeshttps://doi.org/10.1109/tvlsi.2007.893588openalex-snapshot
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses
inferred← citeshttps://doi.org/10.1109/tvlsi.2009.2036267openalex-snapshot
Reliability Analysis and Optimization of Power-Gated ICs
inferred← citeshttps://doi.org/10.1109/ursigass.2014.6929444openalex-snapshot
Power optimization with interconnect repeater heat transferance effect
inferred← citeshttps://doi.org/10.1109/vlsi.2008.85openalex-snapshot
Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/vlsi.design.2010.79openalex-snapshot
Post Assembly Timing Closure for Multi Million Gate Chips
inferred← citeshttps://doi.org/10.1109/vlsisoc.2006.313251openalex-snapshot
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters
inferred← citeshttps://doi.org/10.1109/vlsisoc.2007.4402480openalex-snapshot
Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis
inferred← citeshttps://doi.org/10.1109/vlsisoc.2009.6041341openalex-snapshot
A multistep extrapolated S-parameter model for arbitrary on-chip interconnect structures
inferred← citeshttps://doi.org/10.1145/1055137.1055153openalex-snapshot
A fast algorithm for power grid design
inferred← citeshttps://doi.org/10.1145/1055137.1055177openalex-snapshot
Multilevel generalized force-directed method for circuit placement
inferred← citeshttps://doi.org/10.1145/1059876.1059886openalex-snapshot
Large-scale circuit placement
inferred← citeshttps://doi.org/10.1145/1065579.1065731openalex-snapshot
Microarchitecture-aware floorplanning using a statistical design of experiments approach
inferred← citeshttps://doi.org/10.1145/1119772.1119835openalex-snapshot
Multi-level placement for large-scale mixed-size IC designs
inferred← citeshttps://doi.org/10.1145/1119772.1119914openalex-snapshot
Optimality and scalability study of existing placement algorithms
inferred← citeshttps://doi.org/10.1145/1123008.1123032openalex-snapshot
Efficient generation of short and fast repeater tree topologies
inferred← citeshttps://doi.org/10.1145/1151074.1151076openalex-snapshot
A design methodology for application-specific networks-on-chip
inferred← citeshttps://doi.org/10.1145/1283780.1283866openalex-snapshot
Electromigration and voltage drop aware power grid optimization for power gated ICs
inferred← citeshttps://doi.org/10.1145/1353629.1353648openalex-snapshot
Fast interconnect synthesis with layer assignment
inferred← citeshttps://doi.org/10.1145/1353629.1353649openalex-snapshot
RF interconnects for communications on-chip
inferred← citeshttps://doi.org/10.1145/1629911.1630026openalex-snapshot
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
inferred← citeshttps://doi.org/10.1145/2160916.2160952openalex-snapshot
Towards layout-friendly high-level synthesis
inferred← citeshttps://doi.org/10.1145/2451916.2451942openalex-snapshot
Delay-driven layer assignment in global routing under multi-tier interconnect structure
inferred← citeshttps://doi.org/10.1145/3626184.3635290openalex-snapshot
Scheduling and Physical Design
inferred← citeshttps://doi.org/10.1145/3698364.3712622openalex-snapshot
Invited: Coping with Interconnects
inferred← citeshttps://doi.org/10.1145/378239.379022openalex-snapshot
An interconnect energy model considering coupling effects
inferred← citeshttps://doi.org/10.1145/505388.505399openalex-snapshot
Physical hierarchy generation with routing congestion control
inferred← citeshttps://doi.org/10.1145/505388.505429openalex-snapshot
Timing closure based on physical hierarchy
inferred← citeshttps://doi.org/10.1145/513918.514035openalex-snapshot
Power estimation in global interconnects and its reduction using a novel repeater optimization methodology
inferred← citeshttps://doi.org/10.1145/589411.589438openalex-snapshot
Quadratic deferred-merge embedding algorithm for zero skew clock distribution network
inferred← citeshttps://doi.org/10.1145/775832.775843openalex-snapshot
Microarchitecture evaluation with physical planning
inferred← citeshttps://doi.org/10.1145/775832.775887openalex-snapshot
Multilevel global placement with retiming
inferred← citeshttps://doi.org/10.1145/775832.776046openalex-snapshot
Hybrid hierarchical timing closure methodology for a high performance and low power DSP
inferred← citeshttps://doi.org/10.1145/871506.871527openalex-snapshot
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI
inferred← citeshttps://doi.org/10.1145/981066.981093openalex-snapshot
Topology optimization of structured power/ground networks
inferred← citeshttps://doi.org/10.1145/996566.996585openalex-snapshot
A timing-driven module-based chip design flow
inferred← citeshttps://doi.org/10.1145/996566.996724openalex-snapshot
A method for correcting the functionality of a wire-pipelined circuit
inferred← citeshttps://doi.org/10.5555/1129601.1129624openalex-snapshot
Robust mixed-size placement under tight white-space constraints
inferred← citeshttps://doi.org/10.5555/2840819.2840835openalex-snapshot
TILA: Timing-Driven Incremental Layer Assignment
inferred← citeshttps://doi.org/10.5555/996070.1009895openalex-snapshot
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels
inferred← citeshttps://doi.org/10.5555/996070.1009944openalex-snapshot
A High-level Interconnect Power Model for Design Space Exploration
inferred← citeshttps://doi.org/10.5555/996070.1009948openalex-snapshot
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
inferred← citeshttps://doi.org/10.5555/996070.1009991openalex-snapshot
Large-Scale Circuit Placement: Gap and Promise
inferred← citeshttps://doi.org/10.6100/ir617141openalex-snapshot
Clustered VLIW architectures:a quantitative approach
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