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A design methodology for application-specific networks-on-chip

https://doi.org/10.1145/1151074.1151076
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Guaranteeing the Quality of Services in Networks on Chip
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xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip
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AMBA: enabling reusable on-chip designs
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Exact and efficient crosstalk estimation
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An interconnect-centric design flow for nanometer technologies
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Protocol selection and interface generation for HW-SW codesign
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Physical planning for on-chip multiprocessor networks and switch fabrics
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Next generation CoreConnect/spl trade/ processor local bus architecture
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2008 Asia and South Pacific Design Automation Conference
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New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
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A wave-pipelined on-chip interconnect structure for networks-on-chips
inferredcites →https://doi.org/10.1109/dac.2002.1012729openalex-snapshot
Constraint-driven communication synthesis
inferredcites →https://doi.org/10.1109/date.2003.1253808openalex-snapshot
SPIN: a scalable, packet switched, on-chip micro-network
inferredcites →https://doi.org/10.1109/dsd.2001.952283openalex-snapshot
A comparison of five different multiprocessor SoC bus architectures
inferredcites →https://doi.org/10.1109/hpca.2003.1183554openalex-snapshot
A methodology for designing efficient on-chip interconnects on well-behaved communication patterns
inferredcites →https://doi.org/10.1109/icvd.2004.1261005openalex-snapshot
The Nostrum backbone-a communication protocol stack for Networks on Chip
inferredcites →https://doi.org/10.1109/iscas.2003.1206191openalex-snapshot
Efficient modeling and synthesis of on-chip communication protocols for network-on-chip design
inferredcites →https://doi.org/10.1109/iscas.2005.1464953openalex-snapshot
A Methodology for Design, Modeling, and Analysis of Networks-on-Chip
inferredcites →https://doi.org/10.1109/isvlsi.2002.1016885openalex-snapshot
A network on chip architecture and design methodology
inferredcites →https://doi.org/10.1109/isvlsi18624.2011openalex-snapshot
2011 IEEE Computer Society Annual Symposium on VLSI
inferredcites →https://doi.org/10.1109/jssc.2005.846294openalex-snapshot
IEEE Custom Integrated Circuits Conference
inferredcites →https://doi.org/10.1109/mc.2002.1033027openalex-snapshot
Smart cameras as embedded systems
inferredcites →https://doi.org/10.1109/micro.2002.1176258openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.1109/mm.2002.1044298openalex-snapshot
An interconnect architecture for networking systems on chips
inferredcites →https://doi.org/10.1109/mm.2002.1044299openalex-snapshot
A scalable high-performance computing solution for networks on chips
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/pact17559.2011openalex-snapshot
2011 International Conference on Parallel Architectures and Compilation Techniques
inferredcites →https://doi.org/10.1109/sac.2004.1322614openalex-snapshot
53.2 SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs
inferredcites →https://doi.org/10.1109/sbcci.2001.952994openalex-snapshot
Symposium on Integrated Circuits and Systems Design
inferredcites →https://doi.org/10.1109/tcad.2003.810738openalex-snapshot
Slicing floorplan with clustering constraint
inferredcites →https://doi.org/10.1109/tcad.2004.828127openalex-snapshot
Design Space Exploration for Optimizing On-Chip Communication Architectures
inferredcites →https://doi.org/10.1109/tcsvt.2003.815165openalex-snapshot
Overview of the H.264/AVC video coding standard
inferredcites →https://doi.org/10.1115/1.3258558openalex-snapshot
The 1983 Design Automation Conference
inferredcites →https://doi.org/10.1145/1016720.1016738openalex-snapshot
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/378239.379045openalex-snapshot
Addressing the system-on-a-chip interconnect woes through communication-based design
inferredcites →https://doi.org/10.1145/378239.379046openalex-snapshot
Micronetwork-based integration for SOCs
inferredcites →https://doi.org/10.1145/378239.379048openalex-snapshot
Route packets, net wires
inferredcites →https://doi.org/10.1145/513918.514114openalex-snapshot
Constraint-driven communication synthesis
inferredcites →https://doi.org/10.1145/996566.996809openalex-snapshot
SUNMAP
inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.5555/968879.969208openalex-snapshot
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Pipelined Control-Path Effects On Area And Performance Of A Wormhole-Switched Network-On-Chip
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Flexible Wormhole-Switched Network-On-Chip With Two-Level Priority Data Delivery Service
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Design Challenges in Multiprocessor Systems-on-Chip
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Application Workload and SystemC Platform Modeling for Performance Evaluation
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FONoC: A Fat Tree Based Optical Network-on-Chip for Multiprocessor System-on-Chip
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Design and Analysis of NoCs for Low-Power 2D and 3D SoCs
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3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks
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Platforms and Architectures for Distributed Smart Cameras
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A modeling tool for simulating and design of on-chip network systems
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Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
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A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs
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Custom NoC topology generation using Discrete Antlion Trapping Mechanism
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An energy efficient synthesis flow for application specific SoC design
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Throughput-based network-on-chip topology generation and analysis
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Distributed Shared Memory Architecture for NoC-Based Multi-Processor
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An Efficient Power-Aware Optimization for Task Scheduling on NoC-based Many-core System
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Analytical performance comparison of 2D Mesh, WK-recursive, and Spidergon NoCs
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Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures
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ODOR
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NoC topology synthesis for supporting shutdown of voltage islands in SoCs
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Networks on Chips
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A Predictive NoC Architecture for Vision Systems Dedicated to Image Analysis
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Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management
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3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans
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A Predictive NoC Architecture for Vision Systems Dedicated to Image Analysis
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Energy-efficient design of an asynchronous network-on-chip
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Microarchitecture and Implementation of Networks-on-Chip with a Flexible Concept for Communication Media Sharing
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Novel Power-Aware Optimization Methodology and Efficient Task Scheduling Algorithm
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Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip
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The Effect of Latency Increasing on the Realisation Cost in High Level Synthesis of Pipeline Systems
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Communication flows in power-efficient Networks-on-Chips
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Synthesis of networks on chips for 3D systems on chips
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UNION: a unified inter/intra-chip optical network for chip multiprocessors
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A method to remove deadlocks in networks-on-chips with wormhole flow control
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A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
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SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
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Efficient simulation and modelling of non-rectangular NoC topologies
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Automatic synthesis and optimization of chip multiprocessors
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Efficient simulation and modelling of non-rectangular NoC topologies
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