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The DASH prototype: Logic overhead and performance
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4615-3604-8_9openalex-snapshot
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes*
inferredcites →https://doi.org/10.1109/cmpcon.1988.4913openalex-snapshot
The 4D-MP graphics superworkstation: computing+graphics=40 MIPS+MFLOPS and 100000 lighted polygons per second
inferredcites →https://doi.org/10.1109/isca.1990.134503openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.1990.134519openalex-snapshot
An empirical evaluation of two memory-efficient directory methods
inferredcites →https://doi.org/10.1109/isca.1990.134520openalex-snapshot
The directory-based cache coherence protocol for the DASH multiprocessor
inferredcites →https://doi.org/10.1109/isca.1992.753307openalex-snapshot
The DASH Prototype: Implementation and Performance
inferredcites →https://doi.org/10.1109/tc.1978.1675013openalex-snapshot
A New Solution to Coherence Problems in Multicache Systems
inferredcites →https://doi.org/10.1145/115952.115978openalex-snapshot
Comparative evaluation of latency reducing and tolerating techniques
inferredcites →https://doi.org/10.1145/285930.285987openalex-snapshot
A low-overhead coherence solution for multiprocessors with private cache memories
inferredcites →https://doi.org/10.1145/285930.285997openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/325096.325130openalex-snapshot
An empirical evaluation of two memory-efficient directory methods
inferredcites →https://doi.org/10.1145/325096.325132openalex-snapshot
The directory-based cache coherence protocol for the DASH multiprocessor
inferredcites →https://doi.org/10.1145/800015.808204openalex-snapshot
A low-overhead coherence solution for multiprocessors with private cache memories
inferredcites →https://doi.org/10.21236/ada237629openalex-snapshot
LimitLESS Directories: A Scalable Cache Coherence Scheme
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/(sici)1520-684x(199802)29:2<36::aid-scj5>3.0.co;2-ropenalex-snapshot
Performance evaluation of Two-level Scheduling algorithms for NUMA multiprocessors
inferred← citeshttps://doi.org/10.1006/jpdc.1996.0022openalex-snapshot
Analysis of Multigrid Algorithms on Massively Parallel Computers: Architectural Implications
inferred← citeshttps://doi.org/10.1006/jpdc.1999.1606openalex-snapshot
Comparative Evaluation of Latency-Tolerating and -Reducing Techniques for Hardware-Only and Software-Only Directory Protocols
inferred← citeshttps://doi.org/10.1006/jpdc.2000.1629openalex-snapshot
Parallel Logic Programming Systems on Scalable Architectures
inferred← citeshttps://doi.org/10.1006/rtim.1996.0039openalex-snapshot
Real-Time Image Processing with a MIMD Computer
inferred← citeshttps://doi.org/10.1007/10704826_13openalex-snapshot
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
inferred← citeshttps://doi.org/10.1007/3-540-44862-4_106openalex-snapshot
Parallel DNA Sequence Alignment Using a DSM System in a Cluster of Workstations
inferred← citeshttps://doi.org/10.1007/3-540-45706-2_16openalex-snapshot
Performance of MP3D on the SB-PRAM Prototype
inferred← citeshttps://doi.org/10.1007/3-540-48311-x_211openalex-snapshot
Performance Evaluation of Or-Parallel Logic Programming Systems on Distributed Shared-Memory Architectures⋆
inferred← citeshttps://doi.org/10.1007/3-540-49201-1_9openalex-snapshot
The Influence of Architectural Parameters on the Performance of Parallel Logic Programming Systems
inferred← citeshttps://doi.org/10.1007/3-540-58430-7_1openalex-snapshot
Scalability and programmability of massively parallel processors
inferred← citeshttps://doi.org/10.1007/3-540-61626-8_103openalex-snapshot
Scalability and granularity issues of the hierarchical radiosity method
inferred← citeshttps://doi.org/10.1007/3-540-61626-8_108openalex-snapshot
Shared-memory implementation of an irregular particle simulation method
inferred← citeshttps://doi.org/10.1007/978-1-4471-1011-8_11openalex-snapshot
Parallel Processing for Photo-Realistic Emergency Lighting Visualisation
inferred← citeshttps://doi.org/10.1007/978-1-4615-2698-8_8openalex-snapshot
Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors
inferred← citeshttps://doi.org/10.1007/978-3-662-04303-5_5openalex-snapshot
Parallel Operating Systems
inferred← citeshttps://doi.org/10.1007/bfb0057937openalex-snapshot
Optimising parallel logic programming systems for scalable machines
inferred← citeshttps://doi.org/10.1007/bfb0097971openalex-snapshot
NWCache: Optimizing disk accesses via an optical network/write cache hybrid
inferred← citeshttps://doi.org/10.1016/j.sysarc.2003.08.014openalex-snapshot
A comparative evaluation of hardware-only and software-only directory protocols in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1016/s0045-7906(99)00042-7openalex-snapshot
Evaluation of memory latency in cluster-based cache-coherent multiprocessor systems with different interconnection topologies
inferred← citeshttps://doi.org/10.1016/s0141-9331(99)00029-0openalex-snapshot
A shared memory model on a cluster of PCs
inferred← citeshttps://doi.org/10.1016/s0167-8191(00)00038-7openalex-snapshot
Architecture-independent parallelism for both shared- and distributed-memory machines using the Filaments package
inferred← citeshttps://doi.org/10.1016/s0167-8191(03)00088-7openalex-snapshot
Virtual memory on data diffusion architectures
inferred← citeshttps://doi.org/10.1016/s0304-3975(97)00202-8openalex-snapshot
A shared-memory implementation of the hierarchical radiosity method
inferred← citeshttps://doi.org/10.1016/s0927-5452(06)80007-9openalex-snapshot
Trends in High-Performance Computer Architecture
inferred← citeshttps://doi.org/10.1016/s0928-4869(98)00006-8openalex-snapshot
Execution behavior analysis and performance prediction for a shared-memory implementation of an irregular particle simulation method
inferred← citeshttps://doi.org/10.1016/s1383-7621(02)00066-8openalex-snapshot
Design and analysis of static memory management policies for CC-NUMA multiprocessors
inferred← citeshttps://doi.org/10.1016/s1383-7621(96)00057-4openalex-snapshot
Orchid: A portable platform for parallel programming
inferred← citeshttps://doi.org/10.1023/a:1007941813399openalex-snapshot
Pc-based Shared Memory Architecture and Language
inferred← citeshttps://doi.org/10.1023/a:1008165010732openalex-snapshot
Memory Conscious Scheduling for Cluster-based NUMA Multiprocessors
inferred← citeshttps://doi.org/10.1023/a:1008642513285openalex-snapshot
Load Balancing for Parallel Query Execution on NUMA Multiprocessors
inferred← citeshttps://doi.org/10.1023/a:1018744919483openalex-snapshot
Evaluating the Effect of Coherence Protocols on the Performance of Parallel Programming Constructs
inferred← citeshttps://doi.org/10.1023/a:1018749028569openalex-snapshot
Support for Efficient Programming on the SB-PRAM
inferred← citeshttps://doi.org/10.1109/12.755001openalex-snapshot
An efficient tree cache coherence protocol for distributed shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/2945.537305openalex-snapshot
Analysis of a parallel volume rendering system based on the shear-warp factorization
inferred← citeshttps://doi.org/10.1109/71.388040openalex-snapshot
Distributed hardwired barrier synchronization for scalable multiprocessor clusters
inferred← citeshttps://doi.org/10.1109/71.406963openalex-snapshot
Comparative performance evaluation of hot spot contention between MIN-based and ring-based shared-memory architectures
inferred← citeshttps://doi.org/10.1109/71.476171openalex-snapshot
Comparative modeling and evaluation of CC-NUMA and COMA on hierarchical ring architectures
inferred← citeshttps://doi.org/10.1109/71.770197openalex-snapshot
Resource scaling effects on MPP performance: the STAP benchmark implications
inferred← citeshttps://doi.org/10.1109/71.841740openalex-snapshot
Impact of CC-NUMA memory management policies on the application performance of multistage switching networks
inferred← citeshttps://doi.org/10.1109/arvlsi.1997.634843openalex-snapshot
Scalability in computing for today and tomorrow
inferred← citeshttps://doi.org/10.1109/camp.1997.632030openalex-snapshot
Image processing PCI-based shared memory architecture design
inferred← citeshttps://doi.org/10.1109/cmpcon.1995.512404openalex-snapshot
Tempest: a substrate for portable parallel programs
inferred← citeshttps://doi.org/10.1109/cmpcon.1997.584688openalex-snapshot
System overview of the SGI Origin 200/2000 product line
inferred← citeshttps://doi.org/10.1109/empdp.1996.500567openalex-snapshot
The role of associative memory in virtual shared memory architectures: a price-performance comparison
inferred← citeshttps://doi.org/10.1109/empdp.2003.1183572openalex-snapshot
Computing binary space partition trees using a scope consistent DSM system in a cluster of workstations
inferred← citeshttps://doi.org/10.1109/hicss.1994.323275openalex-snapshot
Using Warp to control network contention in Mermera
inferred← citeshttps://doi.org/10.1109/hicss.1999.772815openalex-snapshot
A shared memory model on a cluster of PCs
inferred← citeshttps://doi.org/10.1109/hicss.1999.773038openalex-snapshot
Defining uniform and hybrid memory consistency models on a unified framework
inferred← citeshttps://doi.org/10.1109/hpca.1995.386539openalex-snapshot
Improving performance by cache driven memory management
inferred← citeshttps://doi.org/10.1109/hpca.1996.501187openalex-snapshot
Multitasking and multithreading on a multiprocessor with virtual shared memory
inferred← citeshttps://doi.org/10.1109/hpca.1997.569606openalex-snapshot
A performance comparison of hierarchical ring- and mesh-connected multiprocessor networks
inferred← citeshttps://doi.org/10.1109/hpca.1997.569660openalex-snapshot
Reducing the communication overhead of dynamic applications on shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/hpdc.1999.805312openalex-snapshot
Using embedded network processors to implement global memory management in a workstation cluster
inferred← citeshttps://doi.org/10.1109/iccd.1995.528917openalex-snapshot
Interrupt-based hardware support for profiling memory system performance
inferred← citeshttps://doi.org/10.1109/iccd.1997.628877openalex-snapshot
A comparative evaluation of hierarchical network architecture of the HP-Convex Exemplar
inferred← citeshttps://doi.org/10.1109/iccsit.2010.5563668openalex-snapshot
Structure research in a sparse directory co-located with last-level cache
inferred← citeshttps://doi.org/10.1109/infcom.2002.1019375openalex-snapshot
Probabilistic location and routing
inferred← citeshttps://doi.org/10.1109/ipdpsw.2010.5470796openalex-snapshot
Memory affinity management for numerical scientific applications over Multi-core Multiprocessors with Hierarchical Memory
inferred← citeshttps://doi.org/10.1109/ipps.1993.262871openalex-snapshot
A multi-level hierarchical cache coherence protocol for multiprocessors
inferred← citeshttps://doi.org/10.1109/ipps.1995.395974openalex-snapshot
Using simple page placement policies to reduce the cost of cache fills in coherent shared-memory systems
inferred← citeshttps://doi.org/10.1109/ipps.1996.508051openalex-snapshot
Implementing the Data Diffusion Machine using crossbar routers
inferred← citeshttps://doi.org/10.1109/ipps.1997.580896openalex-snapshot
DPF: a data parallel Fortran benchmark suite
inferred← citeshttps://doi.org/10.1109/ipps.1997.580946openalex-snapshot
Relative performance of hardware and software-only directory protocols under latency tolerating and reducing techniques
inferred← citeshttps://doi.org/10.1109/ipps.1998.669958openalex-snapshot
Impact of switch design on the application performance of cache-coherent multiprocessors
inferred← citeshttps://doi.org/10.1109/isca.1993.698568openalex-snapshot
Limitations Of Cache Prefetching On A Bus-based Multiprocessor
inferred← citeshttps://doi.org/10.1109/isca.1994.288138openalex-snapshot
Tempest and Typhoon: user-level shared memory
inferred← citeshttps://doi.org/10.1109/isca.1994.288139openalex-snapshot
Software-extended coherent shared memory: performance and cost
inferred← citeshttps://doi.org/10.1109/isca.1994.288160openalex-snapshot
Measurement-based characterization of global memory and network contention, operating system and parallelisation overheads: case study on a shared-memory multiprocessor
inferred← citeshttps://doi.org/10.1109/isca.1994.288162openalex-snapshot
Architectural support for performance tuning: a case study on the SPARCcenter 2000
inferred← citeshttps://doi.org/10.1109/isca.1995.524547openalex-snapshot
Efficient strategies for software-only directory protocols in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1109/isca.1998.694792openalex-snapshot
Design choices in the SHRIMP system: an empirical study
inferred← citeshttps://doi.org/10.1109/isca.1999.765960openalex-snapshot
Scaling application performance on a cache-coherent multiprocessors
inferred← citeshttps://doi.org/10.1109/ispa.2009.69openalex-snapshot
MM-DSM: Multi-threaded Multi-home Distributed Shared Memory Systems
inferred← citeshttps://doi.org/10.1109/jproc.1999.747860openalex-snapshot
Special Issue On Distributed Shared Memory Systems
inferred← citeshttps://doi.org/10.1109/mascot.1994.284429openalex-snapshot
Modeling data migration on CC-NUMA and CC-COMA hierarchical ring architectures
inferred← citeshttps://doi.org/10.1109/micro.2006.28openalex-snapshot
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/pmmpc.1995.504356openalex-snapshot
Facilitating the development of portable parallel applications on distributed memory systems
inferred← citeshttps://doi.org/10.1109/sc.2002.10011openalex-snapshot
SMP System Interconnect Instrumentation for Performance Analysis
inferred← citeshttps://doi.org/10.1109/spdp.1994.346165openalex-snapshot
Eager combining: a coherency protocol for increasing effective network and memory bandwidth in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1142/s012905339900003xopenalex-snapshot
SCALABILITY OF SPARSE CHOLESKY FACTORIZATION
inferred← citeshttps://doi.org/10.1145/1187436.1216586openalex-snapshot
Integrating coordinated checkpointing and recovery mechanisms into DSM synchronization barriers
inferred← citeshttps://doi.org/10.1145/1378533.1378537openalex-snapshot
Combinable memory-block transactions
inferred← citeshttps://doi.org/10.1145/139669.140564openalex-snapshot
Architectural and implementation tradeoffs in the design of multiple-context processors (abstract)
inferred← citeshttps://doi.org/10.1145/165123.165163openalex-snapshot
Limitations of cache prefetching on a bus-based multiprocessor
inferred← citeshttps://doi.org/10.1145/173682.165163openalex-snapshot
Limitations of cache prefetching on a bus-based multiprocessor
inferred← citeshttps://doi.org/10.1145/191995.192016openalex-snapshot
Architectural support for performance tuning: a case study on the SPARCcenter 2000
inferred← citeshttps://doi.org/10.1145/191995.192018openalex-snapshot
Measurement-based characterization of global memory and network contention, operating system and parallelization overheads
inferred← citeshttps://doi.org/10.1145/191995.192060openalex-snapshot
Software-extended coherent shared memory: performance and cost
inferred← citeshttps://doi.org/10.1145/191995.192062openalex-snapshot
Tempest and typhoon: user-level shared memory
inferred← citeshttps://doi.org/10.1145/192007.192016openalex-snapshot
Architectural support for performance tuning
inferred← citeshttps://doi.org/10.1145/192007.192018openalex-snapshot
Measurement-based characterization of global memory and network contention, operating system and parallelization overheads
inferred← citeshttps://doi.org/10.1145/192007.192060openalex-snapshot
Software-extended coherent shared memory
inferred← citeshttps://doi.org/10.1145/192161.192283openalex-snapshot
Fast volume rendering using a shear-warp factorization of the viewing transformation
inferred← citeshttps://doi.org/10.1145/195470.195575openalex-snapshot
Fine-grain access control for distributed shared memory
inferred← citeshttps://doi.org/10.1145/195473.195575openalex-snapshot
Fine-grain access control for distributed shared memory
inferred← citeshttps://doi.org/10.1145/200912.201006openalex-snapshot
Effective cache prefetching on bus-based multiprocessors
inferred← citeshttps://doi.org/10.1145/218327.218331openalex-snapshot
Real-time volume rendering on shared memory multiprocessors using the shear-warp factorization
inferred← citeshttps://doi.org/10.1145/218646.218651openalex-snapshot
A comprehensive bibliography of distributed shared memory
inferred← citeshttps://doi.org/10.1145/223586.223588openalex-snapshot
Memory system performance of UNIX on CC-NUMA multiprocessors
inferred← citeshttps://doi.org/10.1145/223586.223610openalex-snapshot
Scheduling memory constrained jobs on distributed memory parallel computers
inferred← citeshttps://doi.org/10.1145/223587.223588openalex-snapshot
Memory system performance of UNIX on CC-NUMA multiprocessors
inferred← citeshttps://doi.org/10.1145/223587.223610openalex-snapshot
Scheduling memory constrained jobs on distributed memory parallel computers
inferred← citeshttps://doi.org/10.1145/223982.225958openalex-snapshot
Efficient strategies for software-only protocols in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1145/225830.225958openalex-snapshot
Efficient strategies for software-only protocols in shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1145/237090.237185openalex-snapshot
Hiding communication latency and coherence overhead in software DSMs
inferred← citeshttps://doi.org/10.1145/248208.237185openalex-snapshot
Hiding communication latency and coherence overhead in software DSMs
inferred← citeshttps://doi.org/10.1145/248209.237185openalex-snapshot
Hiding communication latency and coherence overhead in software DSMs
inferred← citeshttps://doi.org/10.1145/258492.258513openalex-snapshot
Temporal notions of synchronization and consistency in Beehive
inferred← citeshttps://doi.org/10.1145/263764.263774openalex-snapshot
The interaction of parallel programming constructs and coherence protocols
inferred← citeshttps://doi.org/10.1145/263767.263774openalex-snapshot
The interaction of parallel programming constructs and coherence protocols
inferred← citeshttps://doi.org/10.1145/266670.266687openalex-snapshot
Evaluating parallel logic programming systems on scalable multiprocessors
inferred← citeshttps://doi.org/10.1145/279358.279402openalex-snapshot
Design choices in the SHRIMP system: an empirical study
inferred← citeshttps://doi.org/10.1145/279361.279402openalex-snapshot
Design choices in the SHRIMP system
inferred← citeshttps://doi.org/10.1145/285930.285961openalex-snapshot
Retrospective: the DASH prototype
inferred← citeshttps://doi.org/10.1145/300979.301005openalex-snapshot
Scaling application performance on a cache-coherent multiprocessor
inferred← citeshttps://doi.org/10.1145/307338.301005openalex-snapshot
Scaling application performance on a cache-coherent multiprocessor
inferred← citeshttps://doi.org/10.1145/331697.332322openalex-snapshot
An efficient processor partitioning and thread mapping strategy for mesh-connected multiprocessor systems
inferred← citeshttps://doi.org/10.1145/378420.378810openalex-snapshot
Evaluating the performance of non-blocking synchronization on shared-memory multiprocessors
inferred← citeshttps://doi.org/10.1145/584369.584378openalex-snapshot
Integrating non-blocking synchronisation in parallel applications
inferred← citeshttps://doi.org/10.1155/2002/790749openalex-snapshot
Memory Access Behavior Analysis of NUMA‐Based Shared Memory Programs
inferred← citeshttps://doi.org/10.12720/jcm.14.11.1091-1097openalex-snapshot
Development of Cluster-based Multiprocessor Systems with Analytical Model: A Approach
inferred← citeshttps://doi.org/10.1364/ao.39.006663openalex-snapshot
Disk caching with an optical ring
inferred← citeshttps://doi.org/10.15760/etd.1285openalex-snapshot
Hardware for Fast Global Operations on Distributed Memory Multicomputers and Multiprocessors
inferred← citeshttps://doi.org/10.15760/etd.5858openalex-snapshot
Enhancements to the scalable coherent interface cache protocol
inferred← citeshttps://doi.org/10.35376/10324/104openalex-snapshot
VSR-COMA: Un protocolo de coherencia caché con reemplazo para sistemas multicomputadores con gestión de memoria de tipo COMA
inferred← citeshttps://doi.org/10.5555/762761.762779openalex-snapshot
SMP System Interconnect Instrumentation for Performance Analysis
inferred← citeshttps://doi.org/10.5753/sbac-pad.1994.21886openalex-snapshot
Efeito do Multicasting na Coerência de Cache com Diretórios “Full Map” num Sistema Multiprocessador com Rede Crossbar
inferred← citeshttps://doi.org/10.5753/sbac-pad.1996.19817openalex-snapshot
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