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Fourteen ways to fool your synchronizer
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4615-3990-2openalex-snapshot
Synchronization Design for Digital Systems
inferredcites →https://doi.org/10.1049/piee.1976.0212openalex-snapshot
Synchronisation and arbitration circuits in digital systems
inferredcites →https://doi.org/10.1109/4.341740openalex-snapshot
A fast resolving BiNMOS synchronizer for parallel processor interconnect
inferredcites →https://doi.org/10.1109/4.766819openalex-snapshot
Miller and noise effects in a synchronizing flip-flop
inferredcites →https://doi.org/10.1109/92.386226openalex-snapshot
Investigation into micropipeline latch design styles
inferredcites →https://doi.org/10.1109/async.2003.1199167openalex-snapshot
Timing measurements of synchronization circuits
inferredcites →https://doi.org/10.1109/iccd.1992.276300openalex-snapshot
On limitations and extensions of STG model for designing asynchronous control circuits
inferredcites →https://doi.org/10.1109/jssc.1980.1051359openalex-snapshot
The behaviour of flip-flops used as synchronizers and prediction of their failure rate
inferredcites →https://doi.org/10.1109/t-c.1973.223730openalex-snapshot
Anomalous Behavior of Synchronizer and Arbiter Circuits
inferredcites →https://doi.org/10.1109/tc.1976.5009227openalex-snapshot
Anomalous Response Times of Input Synchronizers
inferredcites →https://doi.org/10.1109/tc.1979.1675337openalex-snapshot
The Anomalous Behavior of Flip-Flops in Synchronizer Circuits
inferredcites →https://doi.org/10.1109/tc.1986.1676806openalex-snapshot
Can Redundancy and Masking Improve the Performance of Synchronizers?
inferredcites →https://doi.org/10.1109/wcadm.1995.514642openalex-snapshot
Single-rail handshake circuits
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Techniques for Improving Design Performance of VLSI Circuits and Systems
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Choice Uncertainty Principle
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Formal Verification of Synchronizers
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Two Efficient Synchronous $\Leftrightarrow$ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures
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Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping
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Power Management Architecture in McNoC
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Asynchronous Communications for NoCs
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Improvements of Pausible Clocking Scheme for High-Throughput and High-Reliability GALS Systems Design
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Asynchronous 3D-NoCs Making Use of Serialized Vertical Links
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GALS Clocking and Shared Interconnect for Large Scale SFQ Systems
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Reliable I/F Circuit for Embedded Self-Timed Data-Driven Processors
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Enabler-Based Synchronizer Model for Clock Domain Crossing Static Verification
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Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings
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Fast Universal Synchronizers
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Muller C-Element Metastability Containment
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Productivity Enhancement in Clock Domain Crossings Verification
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Ramifications of metastability in bit variables explored via Simpson’s 4-slot mechanism
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A predictive synchronizer for periodic clock domains
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Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer
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Acquisition of Asynchronous Data
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Network Interface Architecture and Design Issues
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Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
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Performance Evaluation of Elastic GALS Interfaces and Network Fabric
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Metastability tests of flip–flops in programmable digital circuits
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Truncation error analysis of MTBF computation for multi-latch synchronizers
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A high performance dual clock elastic FIFO network interface for GALS NoC
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A hardwired NoC infrastructure for embedded systems on FPGAs
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Two efficient synchronous asynchronous converters well-suited for networks-on-chip in GALS architectures
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A new FIFO for transferring data between two unrelated clock domains
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Face-to-face bus design with built-in self-test in 3D ICs
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The Communication and Computation Architecture for a Universal Space Robotic Joint
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The Devolution of Synchronizers
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MTBF Estimation in Coherent Clock Domains
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A novel asynchronous first-in-first-out adapting to multi-synchronous network-on-chips
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Analysis of Resistive Bridging Defects in a Synchronizer
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Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip
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Design of a GALS Wrapper for Network on Chip
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Computing Synchronizer Failure Probabilities
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Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA
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SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
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Analysis and optimization of pausible clocking based GALS design
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Lowering the latency of interfaces for rationally-related frequencies
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Analysis of Synchronizer, Data Loss and Occurrence of Metastability
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An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip
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Metastability in asynchronous wait-free protocols
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Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains
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Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs
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An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique
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A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems
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Port controller for GALS with first come first served function
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A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems
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Synchronization Techniques for Crossing Multiple Clock Domains in FPGA-Based TMR Circuits
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Toward a multiple clock/voltage island design style for power-aware processors
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GALDS: a complete framework for designing multiclock ASICs and SoCs
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Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains
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Eleven Ways to Boost Your Synchronizer
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Conclusively verifying clock-domain crossings in very large hardware designs
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Multiple reset domains verification using assertion based verification
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Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links
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System level power and performance modeling of GALS point-to-point communication interfaces
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A survey of research and practices of Network-on-chip
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Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs
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Early set to zero micro-pipeline
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VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation
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Automated Verification and Clock Frequency Characteristics in CDC Solution
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Studies and a Method to Minimize and Control the Jitter in Optical Based Communication System
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Static Analysis and Verification of Aerospace Software by Abstract Interpretation
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Static Analysis and Verification of Aerospace Software by Abstract Interpretation
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GALS design methodology based on pausible clocking
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Finite State Machine Datapath Design, Optimization, and Implementation
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Design and implementation of clocked open core protocol interfaces for intellectual property cores and on-chip network fabric
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GALS system design: Side channel attack secure cryptographic accelerators
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An Asynchronous Interface with Robust Control for Globally-Asynchronous Locally-Synchronous Systems
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Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains
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Design of an Asynchronous Switch for Clock Domain Crossing Interfaces
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An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
inferred← citeshttps://doi.org/10.5555/1266366.1266663openalex-snapshot
Computing synchronizer failure probabilities
inferred← citeshttps://doi.org/10.5555/1266366.1266668openalex-snapshot
Clock domain crossing fault model and coverage metric for validation of SoC design
inferred← citeshttps://doi.org/10.5555/2485288.2485694openalex-snapshot
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools
inferred← citeshttps://doi.org/10.5555/2492708.2492811openalex-snapshot
Test generation for clock-domain crossing faults in integrated circuits
inferred← citeshttps://doi.org/10.5573/jsts.2015.15.2.208openalex-snapshot
Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains
inferred← citeshttps://doi.org/10.82308/37390openalex-snapshot
Modeling, evaluation, and implementation of ring-based interconnects for network-on-chip
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