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A survey of research and practices of Network-on-chip

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1006/jcss.2000.1701openalex-snapshot

On the Benefit of Supporting Virtual Channels in Wormhole Routers

inferredcites →https://doi.org/10.1007/0-306-48727-6_8openalex-snapshot

Clocking Strategies for Networks-on-Chip

inferredcites →https://doi.org/10.1007/978-1-4020-6488-3_8openalex-snapshot

Networks on Chips

inferredcites →https://doi.org/10.1007/978-1-4757-3385-3openalex-snapshot

Principles of Asynchronous Circuit Design

inferredcites →https://doi.org/10.1007/978-3-540-30205-6_32openalex-snapshot

A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling

inferredcites →https://doi.org/10.1007/b105353openalex-snapshot

Networks on Chip

inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.003openalex-snapshot

Interconnect intellectual property for Network-on-Chip (NoC)

inferredcites →https://doi.org/10.1016/j.sysarc.2003.07.004openalex-snapshot

QNoC: QoS architecture and design process for network on chip

inferredcites →https://doi.org/10.1016/j.vlsi.2004.03.003openalex-snapshot

HERMES: an infrastructure for low area overhead packet-switching networks on chip

inferredcites →https://doi.org/10.1016/j.vlsi.2004.07.015openalex-snapshot

Issues in the development of a practical NoC: the Proteo concept

inferredcites →https://doi.org/10.1016/s0167-8191(00)00027-2openalex-snapshot

Contention-free communication scheduling for array redistribution

inferredcites →https://doi.org/10.1016/s1386-9477(02)00686-0openalex-snapshot

Optical interconnects for future high performance integrated circuits

inferredcites →https://doi.org/10.1049/ip-cdt:20045093openalex-snapshot

Asynchronous on-chip networks

inferredcites →https://doi.org/10.1109/12.506422openalex-snapshot

Distributed, deadlock-free routing in faulty, pipelined, direct interconnection networks

inferredcites →https://doi.org/10.1109/12.53599openalex-snapshot

Performance analysis of k-ary n-cube interconnection networks

inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot

Networks on chips: a new SoC paradigm

inferredcites →https://doi.org/10.1109/4.475712openalex-snapshot

Regenerative feedback repeaters for programmable interconnections

inferredcites →https://doi.org/10.1109/4.933468openalex-snapshot

Optimum voltage swing on on-chip and off-chip interconnect

inferredcites →https://doi.org/10.1109/40.903059openalex-snapshot

A delay model for router microarchitectures

inferredcites →https://doi.org/10.1109/43.828553openalex-snapshot

A global wiring paradigm for deep submicron design

inferredcites →https://doi.org/10.1109/5.362752openalex-snapshot

Asynchronous design methodologies: an overview

inferredcites →https://doi.org/10.1109/5.920580openalex-snapshot

The future of wires

inferredcites →https://doi.org/10.1109/5.929646openalex-snapshot

High-performance interconnects: an integration overview

inferredcites →https://doi.org/10.1109/65.580917openalex-snapshot

A survey and comparison of wormhole routing techniques in a mesh networks

inferredcites →https://doi.org/10.1109/71.127260openalex-snapshot

Virtual-channel flow control

inferredcites →https://doi.org/10.1109/71.219761openalex-snapshot

Deadlock-free adaptive routing in multicomputer networks using virtual channels

inferredcites →https://doi.org/10.1109/71.250114openalex-snapshot

A new theory of deadlock-free adaptive routing in wormhole networks

inferredcites →https://doi.org/10.1109/71.473515openalex-snapshot

A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks

inferredcites →https://doi.org/10.1109/71.532115openalex-snapshot

A necessary and sufficient condition for deadlock-free routing in cut-through and store-and-forward networks

inferredcites →https://doi.org/10.1109/71.877831openalex-snapshot

The odd-even turn model for adaptive routing

inferredcites →https://doi.org/10.1109/71.910875openalex-snapshot

Impact of virtual channels and adaptive routing on application performance

inferredcites →https://doi.org/10.1109/71.970556openalex-snapshot

A general theory for deadlock-free adaptive routing using a mixed set of resources

inferredcites →https://doi.org/10.1109/92.845893openalex-snapshot

Low-swing on-chip signaling techniques: effectiveness and robustness

inferredcites →https://doi.org/10.1109/async.2000.836791openalex-snapshot

Practical design of globally-asynchronous locally-synchronous systems

inferredcites →https://doi.org/10.1109/async.2000.837017openalex-snapshot

High-throughput asynchronous pipelines for fine-grain dynamic datapaths

inferredcites →https://doi.org/10.1109/async.2001.914075openalex-snapshot

Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

inferredcites →https://doi.org/10.1109/async.2003.1199169openalex-snapshot

Fourteen ways to fool your synchronizer

inferredcites →https://doi.org/10.1109/async.2004.1299298openalex-snapshot

Data synchronization issues in GALS SoCs

inferredcites →https://doi.org/10.1109/async.2005.10openalex-snapshot

An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework

inferredcites →https://doi.org/10.1109/async.2005.11openalex-snapshot

An Asynchronous Router for Multiple Service Levels Networks on Chip

inferredcites →https://doi.org/10.1109/async.2005.7openalex-snapshot

A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip

inferredcites →https://doi.org/10.1109/date.2002.998309openalex-snapshot

Networks on silicon: combining best-effort and guaranteed services

inferredcites →https://doi.org/10.1109/date.2005.1openalex-snapshot

×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips

inferredcites →https://doi.org/10.1109/date.2005.11openalex-snapshot

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification

inferredcites →https://doi.org/10.1109/date.2005.33openalex-snapshot

A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips

inferredcites →https://doi.org/10.1109/date.2005.36openalex-snapshot

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

inferredcites →https://doi.org/10.1109/dsd.2002.1115369openalex-snapshot

Networks on silicon: blessing or nightmare?

inferredcites →https://doi.org/10.1109/hpca.2000.824340openalex-snapshot

Flit-reservation flow control

inferredcites →https://doi.org/10.1109/icasic.2003.1277494openalex-snapshot

Design of a switching node (router) for on-chip networks

inferredcites →https://doi.org/10.1109/iccad.2004.1382601openalex-snapshot

Application-specific buffer space allocation for networks-on-chip router design

inferredcites →https://doi.org/10.1109/iccd.2012.6378615openalex-snapshot

Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs

inferredcites →https://doi.org/10.1109/icm.2003.238427openalex-snapshot

An asynchronous low latency arbiter for Quality of Service (QoS) applications

inferredcites →https://doi.org/10.1109/icvd.1995openalex-snapshot

Proceedings of the 8th International Conference on VLSI Design

inferredcites →https://doi.org/10.1109/icvd.2001.902636openalex-snapshot

Evaluation of the traffic-performance characteristics of system-on-chip communication architectures

inferredcites →https://doi.org/10.1109/icvd.2003.1183166openalex-snapshot

Interfacing cores with on-chip packet-switched networks

inferredcites →https://doi.org/10.1109/iitc.1998.704739openalex-snapshot

On-chip interconnects: giga hertz and beyond

inferredcites →https://doi.org/10.1109/ipdps.2002.1015559openalex-snapshot

Hierarchical interconnects for on-chip clustering

inferredcites →https://doi.org/10.1109/isca.1988.5245openalex-snapshot

High-performance multiqueue buffers for VLSI communication switches

inferredcites →https://doi.org/10.1109/isca.1990.134508openalex-snapshot

Virtual-channel flow control

inferredcites →https://doi.org/10.1109/iscas.1999.780794openalex-snapshot

Globally asynchronous locally synchronous architecture for large high-performance ASICs

inferredcites →https://doi.org/10.1109/iscas.2003.1206235openalex-snapshot

Design of a switch for network on chip applications

inferredcites →https://doi.org/10.1109/iscas.2005.1464950openalex-snapshot

Network-on-Chip-Centric Approach to Interleaving in High Throughput Channel Decoders

inferredcites →https://doi.org/10.1109/iscas.2005.1464951openalex-snapshot

Power analysis of link level and end-to-end data protection in networks on chip

inferredcites →https://doi.org/10.1109/iscas.2005.1464952openalex-snapshot

Effect of Traffic Localization on Energy Dissipation in NoC-based Interconnect

inferredcites →https://doi.org/10.1109/iscas.2005.1464953openalex-snapshot

A Methodology for Design, Modeling, and Analysis of Networks-on-Chip

inferredcites →https://doi.org/10.1109/iscas.2005.1465097openalex-snapshot

Slack-Time Aware Routing in NoC Systems

inferredcites →https://doi.org/10.1109/iscas.2005.1465098openalex-snapshot

An Arbitration Look-Ahead Scheme for Reducing End-to-End Latency in Networks on chip

inferredcites →https://doi.org/10.1109/iscas.2005.1465099openalex-snapshot

Self-Calibrating Networks-On-Chip

inferredcites →https://doi.org/10.1109/iscas.2005.1465100openalex-snapshot

A Novel Approach for Network on Chip Emulation

inferredcites →https://doi.org/10.1109/iscas.2005.1465101openalex-snapshot

A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on-Chip

inferredcites →https://doi.org/10.1109/isscc.2000.839694openalex-snapshot

A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications

inferredcites →https://doi.org/10.1109/isscc.2001.912667openalex-snapshot

Elastic interconnects: repeater-inserted long wiring capable of compressing and decompressing data

inferredcites →https://doi.org/10.1109/isscc.2001.912693openalex-snapshot

The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor

inferredcites →https://doi.org/10.1109/isscc.2003.1234326openalex-snapshot

A clock skew absorbing flip-flop

inferredcites →https://doi.org/10.1109/issoc.2005.1595670openalex-snapshot

An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip

inferredcites →https://doi.org/10.1109/isvlsi.2002.1016885openalex-snapshot

A network on chip architecture and design methodology

inferredcites →https://doi.org/10.1109/isvlsi.2004.1339507openalex-snapshot

Fault tolerant algorithms for network-on-chip interconnect

inferredcites →https://doi.org/10.1109/isvlsi.2005.40openalex-snapshot

Proceedings. IEEE Computer Society Annual Symposium on VLSI

inferredcites →https://doi.org/10.1109/mdt.2005.99openalex-snapshot

Æthereal Network on Chip:Concepts, Architectures, and Implementations

inferredcites →https://doi.org/10.1109/mm.2002.1044296openalex-snapshot

Chain: a delay-insensitive chip area interconnect

inferredcites →https://doi.org/10.1109/mm.2002.1044298openalex-snapshot

An interconnect architecture for networking systems on chips

inferredcites →https://doi.org/10.1109/mm.2002.1044299openalex-snapshot

A scalable high-performance computing solution for networks on chips

inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot

The Raw microprocessor: a computational fabric for software circuits and general-purpose programs

inferredcites →https://doi.org/10.1109/mwsym.1997.602823openalex-snapshot

Thin-film microstrip lines for MM and sub-MM/wave on-chip interconnects

inferredcites →https://doi.org/10.1109/norchp.2004.1423874openalex-snapshot

On improving best-effort throughput by better utilization of guaranteed throughput channels in an on-chip communication system

inferredcites →https://doi.org/10.1109/pact.2001openalex-snapshot

Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques

inferredcites →https://doi.org/10.1109/real.2003.1253273openalex-snapshot

Network-on-chip modeling for system-level multiprocessor simulation

inferredcites →https://doi.org/10.1109/socc.2004.1362432openalex-snapshot

An asynchronous on-chip network router with quality-of-service (QoS) support

inferredcites →https://doi.org/10.1109/tc.1985.6312192openalex-snapshot

Fat-trees: Universal networks for hardware-efficient supercomputing

inferredcites →https://doi.org/10.1109/tc.1987.1676939openalex-snapshot

Deadlock-Free Message Routing in Multiprocessor Interconnection Networks

inferredcites →https://doi.org/10.1109/tpds.2005.22openalex-snapshot

NoC synthesis flow for customized domain specific multiprocessor systems-on-chip

inferredcites →https://doi.org/10.1109/tvlsi.2004.830919openalex-snapshot

An architecture and compiler for scalable on-chip communication

inferredcites →https://doi.org/10.1109/vlsic.1996.507748openalex-snapshot

A 50% noise reduction interface using low-weight coding

inferredcites →https://doi.org/10.1109/vlsic.2003.1221224openalex-snapshot

Efficient on-chip global interconnects

inferredcites →https://doi.org/10.1145/1028176.1006717openalex-snapshot

Low-Latency Virtual-Channel Routers for On-Chip Networks

inferredcites →https://doi.org/10.1145/1084834.1084857openalex-snapshot

A unified approach to constrained mapping and routing on network-on-chip architectures

inferredcites →https://doi.org/10.1145/1084834.1084858openalex-snapshot

Spatial division multiplexing

inferredcites →https://doi.org/10.1145/1120725.1120741openalex-snapshot

MAIA

inferredcites →https://doi.org/10.1145/185675.185682openalex-snapshot

The turn model for adaptive routing

inferredcites →https://doi.org/10.1145/290409.290412openalex-snapshot

A quantitative comparison of parallel computation models

inferredcites →https://doi.org/10.1145/337292.337561openalex-snapshot

Communication architecture tuners

inferredcites →https://doi.org/10.1145/339647.339673openalex-snapshot

Smart Memories

inferredcites →https://doi.org/10.1145/343647.343776openalex-snapshot

A generic architecture for on-chip packet-switched interconnections

inferredcites →https://doi.org/10.1145/378239.378256openalex-snapshot

Robust interfaces for mixed-timing systems with application to latency-insensitive protocols

inferredcites →https://doi.org/10.1145/378239.379047openalex-snapshot

On-chip communication architecture for OC-768 network processors

inferredcites →https://doi.org/10.1145/378239.379048openalex-snapshot

Route packets, net wires

inferredcites →https://doi.org/10.1145/383082.383126openalex-snapshot

Encodings for high-performance for energy-efficient signaling

inferredcites →https://doi.org/10.1145/500001.500009openalex-snapshot

Powering networks on chips

inferredcites →https://doi.org/10.1145/513918.514116openalex-snapshot

Traffic analysis for on-chip networks design of multimedia applications

inferredcites →https://doi.org/10.1145/566408.566462openalex-snapshot

Future directions in clocking multi-ghz systems

inferredcites →https://doi.org/10.1145/633625.52439openalex-snapshot

High-performance multi-queue buffers for VLSI communications switches

inferredcites →https://doi.org/10.1145/944645.944694openalex-snapshot

A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip

inferredcites →https://doi.org/10.1145/966747.966758openalex-snapshot

Topology optimization for application-specific networks-on-chip

inferredcites →https://doi.org/10.1145/996566.996809openalex-snapshot

SUNMAP

inferredcites →https://doi.org/10.13140/rg.2.1.4128.7843openalex-snapshot

Globally-Asynchronous Locally-Synchronous Systems

inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot

Orion: a power-performance simulator for interconnection networks

inferredcites →https://doi.org/10.5555/789083.1022751openalex-snapshot

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

inferredcites →https://doi.org/10.5555/789083.1022885openalex-snapshot

Micro-Network for SoC: Implementation of a 32-Port SPIN network

inferredcites →https://doi.org/10.5555/882452.874338openalex-snapshot

Managing power consumption in networks on chips

inferredcites →https://doi.org/10.5555/968878.969037openalex-snapshot

Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints

inferredcites →https://doi.org/10.5555/968879.969127openalex-snapshot

Cost-performance trade-offs in networks on chip: a simulation-based approach

inferredcites →https://doi.org/10.5555/968879.969205openalex-snapshot

An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

inferredcites →https://doi.org/10.5555/968879.969207openalex-snapshot

Bandwidth-constrained mapping of cores onto NoC architectures

inferredcites →https://doi.org/10.5555/968879.969208openalex-snapshot

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

inferredcites →https://doi.org/10.5555/968879.969213openalex-snapshot

System Verilog for VHDL Users

inferredcites →https://doi.org/10.7551/mitpress/1425.003.0025openalex-snapshot

Performance Analysis of k-ary n-cube Interconnection Networks

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.3217/jucs-018-07-0937openalex-extracted

Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach

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Semantic Analysis for Multimedia Security Application

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Tracking of Objects of Interest in a Sequence of Images

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A Reconfigurable On‐Chip Interconnection Network for Large Multicore Systems

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Overview of Biomedical Image Understanding Methods

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Detection of Moving Violations

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Video Anomaly Detection

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Microelectronic System Design in the Field of Time‐Average‐Frequency: A Paradigm Shift

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A Case Study on Cluster Based Application Mapping Method for Power Optimization in 2D NoC

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ASIP‐Based Multi‐Processor Systems for an Efficient Implementation of CNNs

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A crime reports analysis system to identify related crimes

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Internet‐based instructional resource exposing middle school students to structural and earthquake engineering

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Developing the TriLab, a triple access mode (hands‐on, virtual, remote) laboratory, of a process control rig using LabVIEW and Joomla

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Computational simulations as virtual laboratories for online engineering education: A case study in the field of thermoelectricity

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A web‐based design and assessment tool for educational wireless networking projects

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Association analysis of moodle e‐tests in blended learning educational environment

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The File Mover: high‐performance data transfer for the grid

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A toolkit for modelling and simulating data Grids: an extension to GridSim

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CAP Bench: a benchmark suite for performance and energy evaluation of low‐power many‐core processors

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FPGA‐Based GRU Accelerator for Streaming Data Processing

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Applying Kolb's Experiential Learning Cycle for Laboratory Education

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Student Perceptions of Learning in the Laboratory: Comparison of Industrially Situated Virtual Laboratories to Capstone Physical Laboratories

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Characterizing network traffic behaviour using granule‐based association rule mining

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Student learning in science simulations: Design features that promote learning gains

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An adaptive kernel‐based target tracking method based on multiple features fusion

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Bio‐inspired network on chip having both guaranteed throughput and best effort services using fault‐tolerant algorithm

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Revisiting evolutionary algorithms in feature selection and nonfuzzy/fuzzy rule based classification

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Moving Object Detection and Tracking in Wide Area Motion Imagery

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QoS in Networks-on-Chip – Beyond Priority and Circuit Switching Techniques

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Simulation-Based Innovization Using Data Mining for Production Systems Analysis

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Stochastic Communication in Application Specific Networks—on—Chip

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Automatic Video Surveillance of Harbour Structures

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Multiprocessor System-on-Chip

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An Introduction to Multi-Core System on Chip – Trends and Challenges

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Proposed Solution

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Asynchronous Communications for NoCs

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Networks-on-Chip (NoC)

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Techniques for High Performance Noc Routing

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Performance-Energy Tradeoffs for Noc Reliability

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Bidirectional Noc Architecture

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Blogging Around the Globe: Motivations, Privacy Concerns, and Social Networking

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Person Re-identification: System Design and Evaluation Overview

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Benchmarking Network-on-Chip (NoC) Designs

inferred← citeshttps://doi.org/10.1007/978-1-4614-0791-1_10openalex-snapshot

Concluding Remarks

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NoC Basics

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Adaptability: The Key for Future Embedded Systems

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Reconfigurable Intercommunication Infrastructure: NoCs

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A Perceptual System for Language Game Experiments

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Fault-Tolerant Reconfigurable On-Chip-Network

inferred← citeshttps://doi.org/10.1007/978-1-4614-4274-5_1openalex-snapshot

Network-on-Chip Technology: A Paradigm Shift

inferred← citeshttps://doi.org/10.1007/978-1-4614-4274-5_2openalex-snapshot

NoC Modeling and Topology Exploration

inferred← citeshttps://doi.org/10.1007/978-1-4614-7010-6_51openalex-snapshot

An Object Tracking Approach Based on Hu Moments and ABCshift

inferred← citeshttps://doi.org/10.1007/978-1-4614-7864-5_7openalex-snapshot

Related Work and Outlook

inferred← citeshttps://doi.org/10.1007/978-1-84882-229-0_8openalex-snapshot

Network Evolution: Theory and Mechanisms

inferred← citeshttps://doi.org/10.1007/978-1-84882-409-6_1openalex-snapshot

Overview – Parallel Computing: Numerics, Applications, and Trends

inferred← citeshttps://doi.org/10.1007/978-3-030-04224-0_38openalex-snapshot

Deep Adaptive Update of Discriminant KCF for Visual Tracking

inferred← citeshttps://doi.org/10.1007/978-3-030-13940-7_10openalex-snapshot

Using the Monge-Kantorovitch Transform in Chromagenic Color Constancy for Pathophysiology

inferred← citeshttps://doi.org/10.1007/978-3-030-22815-6_40openalex-snapshot

A Robust Long-Term Pedestrian Tracking-by-Detection Algorithm Based on Three-Way Decision

inferred← citeshttps://doi.org/10.1007/978-3-030-23987-9_4openalex-snapshot

Discrete Regular Polygons for Digital Shape Rigid Motion via Polygonization

inferred← citeshttps://doi.org/10.1007/978-3-030-26773-5_5openalex-snapshot

Fuzzy Confirmation Measures (a)symmetry Properties

inferred← citeshttps://doi.org/10.1007/978-3-030-31310-4_1openalex-snapshot

Introduction

inferred← citeshttps://doi.org/10.1007/978-3-030-35396-4_10openalex-snapshot

A Comparison of Student Perceptions of Physical and Virtual Engineering Laboratory Classes

inferred← citeshttps://doi.org/10.1007/978-3-030-43306-2_113openalex-snapshot

Three-Dimensional Human Motion Simulation and Video Analysis System for Physical Training

inferred← citeshttps://doi.org/10.1007/978-3-030-57524-3_8openalex-snapshot

Distorted Probabilities and Bayesian Confirmation Measures

inferred← citeshttps://doi.org/10.1007/978-3-030-58475-7_34openalex-snapshot

In Pursuit of an Efficient SAT Encoding for the Hamiltonian Cycle Problem

inferred← citeshttps://doi.org/10.1007/978-3-030-65661-4_3openalex-snapshot

Analysis of Target Detection and Tracking for Intelligent Vision System

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_1openalex-snapshot

Trustworthy System-on-Chip Design Using Secure on-Chip Communication Architectures

inferred← citeshttps://doi.org/10.1007/978-3-030-76841-6_7openalex-snapshot

Employing Authentic Analytics for More Authentic Tasks

inferred← citeshttps://doi.org/10.1007/978-3-030-79457-6_13openalex-snapshot

Combining Siamese Network and Correlation Filter for Complementary Object Tracking

inferred← citeshttps://doi.org/10.1007/978-3-031-28180-8_24openalex-snapshot

A Deadlock-Free and Adaptive Prime Perspective Turn Model for 3D-Mesh Based Network-on-Chips

inferred← citeshttps://doi.org/10.1007/978-3-031-57873-1_4openalex-snapshot

Scalable Architectures of Neuromorphic Computing

inferred← citeshttps://doi.org/10.1007/978-3-031-85012-7_6openalex-snapshot

History for Understanding the Present

inferred← citeshttps://doi.org/10.1007/978-3-031-97709-1_23openalex-snapshot

Implementation of Wormhole Switching with Virtual Channels to Mitigate Deadlock

inferred← citeshttps://doi.org/10.1007/978-3-032-26370-4_19openalex-snapshot

Performance Analysis of Machine Learning-Based Network-on-Chip (NoC) Topologies

inferred← citeshttps://doi.org/10.1007/978-3-032-30491-9_24openalex-snapshot

A Systematic Literature Review of Network-on-Chip Architectures: Topologies, Routing, Reliability, and Emerging Technologies

inferred← citeshttps://doi.org/10.1007/978-3-319-01604-7_13openalex-snapshot

Named Entity Recognition in Turkish with Bayesian Learning and Hybrid Approaches

inferred← citeshttps://doi.org/10.1007/978-3-319-04184-1_2openalex-snapshot

Background and Literature Review

inferred← citeshttps://doi.org/10.1007/978-3-319-04942-7_9openalex-snapshot

Design Exploration Methodology for Microprocessor and HW Accelerators

inferred← citeshttps://doi.org/10.1007/978-3-319-05476-6_53openalex-snapshot

Multiple Object Tracking Based on a Hierarchical Clustering of Features Approach

inferred← citeshttps://doi.org/10.1007/978-3-319-06028-6_97openalex-snapshot

Column Stores as an IR Prototyping Tool

inferred← citeshttps://doi.org/10.1007/978-3-319-06608-0_2openalex-snapshot

Extracting Diverse Patterns with Unbalanced Concept Hierarchy

inferred← citeshttps://doi.org/10.1007/978-3-319-07308-8_15openalex-snapshot

How Does User’s Access to Object Make HCI Smooth in Recipe Guidance?

inferred← citeshttps://doi.org/10.1007/978-3-319-07617-1_18openalex-snapshot

Evaluation of Bounding Box Level Fusion of Single Target Video Object Trackers

inferred← citeshttps://doi.org/10.1007/978-3-319-08239-4_11openalex-snapshot

Static and Dynamic Mapping Heuristics for Multiprocessor Systems-on-Chip

inferred← citeshttps://doi.org/10.1007/978-3-319-10584-0_35openalex-snapshot

Robust Foreground Detection Using Smoothness and Arbitrariness Constraints

inferred← citeshttps://doi.org/10.1007/978-3-319-10849-0_8openalex-snapshot

Incremental Discriminative Color Object Tracking

inferred← citeshttps://doi.org/10.1007/978-3-319-11331-9_48openalex-snapshot

Depth Map’s 2D Histogram Assisted Occlusion Handling in Video Object Tracking

inferred← citeshttps://doi.org/10.1007/978-3-319-11430-9_2openalex-snapshot

Human Action Recognition: Contour-Based and Silhouette-Based Approaches

inferred← citeshttps://doi.org/10.1007/978-3-319-11740-9_29openalex-snapshot

Online Object Tracking via Collaborative Model within the Cascaded Feedback Framework

inferred← citeshttps://doi.org/10.1007/978-3-319-11933-5_36openalex-snapshot

Moving Object Detection by Fuzzy Aggregation Using Low Rank Weightage Representation

inferred← citeshttps://doi.org/10.1007/978-3-319-12027-0_27openalex-snapshot

An Algorithm to Condense Social Networks and Identify Brokers

inferred← citeshttps://doi.org/10.1007/978-3-319-16214-0_14openalex-snapshot

Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays

inferred← citeshttps://doi.org/10.1007/978-3-319-16214-0_16openalex-snapshot

Survey on Real-Time Network-on-Chip Architectures

inferred← citeshttps://doi.org/10.1007/978-3-319-16354-3_82openalex-snapshot

Reproducible Experiments on Lexical and Temporal Feedback for Tweet Search

inferred← citeshttps://doi.org/10.1007/978-3-319-16631-5_16openalex-snapshot

Debugging Object Tracking Results by a Recommender System with Correction Propagation

inferred← citeshttps://doi.org/10.1007/978-3-319-16814-2_34openalex-snapshot

Boosting-Based Visual Tracking Using Structural Local Sparse Descriptors

inferred← citeshttps://doi.org/10.1007/978-3-319-17822-6_16openalex-snapshot

Polynomial Approximation to Well-Founded Semantics for Logic Programs with Generalized Atoms: Case Studies

inferred← citeshttps://doi.org/10.1007/978-3-319-19264-2_12openalex-snapshot

Rotation Invariant Tracking Algorithm Based on Circular HOGs

inferred← citeshttps://doi.org/10.1007/978-3-319-19545-2_1openalex-snapshot

Quantitative Redundancy in Partial Implications

inferred← citeshttps://doi.org/10.1007/978-3-319-20071-2_7openalex-snapshot

Low-Power NoC Using Optimum Adaptation

inferred← citeshttps://doi.org/10.1007/978-3-319-23117-4_18openalex-snapshot

Multiple Hypothesis Tracking with Sign Language Hand Motion Constraints

inferred← citeshttps://doi.org/10.1007/978-3-319-23497-7_3openalex-snapshot

Exploiting “Mental” Images in Artificial Neural Network Computation

inferred← citeshttps://doi.org/10.1007/978-3-319-24004-6_4openalex-snapshot

The Reconfigurable Cell Array

inferred← citeshttps://doi.org/10.1007/978-3-319-26181-2_23openalex-snapshot

Tracking and Identifying a Changing Appearance Target

inferred← citeshttps://doi.org/10.1007/978-3-319-26535-3_12openalex-snapshot

Discovery of Interesting Association Rules Using Genetic Algorithm with Adaptive Mutation

inferred← citeshttps://doi.org/10.1007/978-3-319-28228-2_4openalex-snapshot

The Picat-SAT Compiler

inferred← citeshttps://doi.org/10.1007/978-3-319-28971-7_23openalex-snapshot

Context-Based Situation Recognition in Computer Vision Systems

inferred← citeshttps://doi.org/10.1007/978-3-319-32034-2_58openalex-snapshot

Discovery of Genes Implied in Cancer by Genetic Algorithms and Association Rules

inferred← citeshttps://doi.org/10.1007/978-3-319-41501-7_46openalex-snapshot

A Lightweight Face Tracking System for Video Surveillance

inferred← citeshttps://doi.org/10.1007/978-3-319-41706-6_9openalex-snapshot

Advances in Exploratory Pattern Analytics on Ubiquitous Data and Social Media

inferred← citeshttps://doi.org/10.1007/978-3-319-45656-0_10openalex-snapshot

Monotonicity and Symmetry of IFPD Bayesian Confirmation Measures

inferred← citeshttps://doi.org/10.1007/978-3-319-48890-5_4openalex-snapshot

On Combining Compressed Sensing and Sparse Representations for Object Tracking

inferred← citeshttps://doi.org/10.1007/978-3-319-60753-5_3openalex-snapshot

Tracking Movement Target by Using WebGIS on Video Surveillance System

inferred← citeshttps://doi.org/10.1007/978-3-319-64352-6_34openalex-snapshot

Spatial Learning of Novice Engineering Students Through Practice of Interaction with Robot-Manipulators

inferred← citeshttps://doi.org/10.1007/978-3-319-64352-6_36openalex-snapshot

The VISIR+ Project – Preliminary Results of the Training Actions

inferred← citeshttps://doi.org/10.1007/978-3-319-66158-2_43openalex-snapshot

Optimizing SAT Encodings for Arithmetic Constraints

inferred← citeshttps://doi.org/10.1007/978-3-319-69832-8_4openalex-snapshot

Generator Platform of Benchmark Time-Lapsed Images Development of Cell Tracking Algorithms: Implementation of New Features Towards a Realistic Simulation of the Cell Spatial and Temporal Organization

inferred← citeshttps://doi.org/10.1007/978-3-319-69835-9_63openalex-snapshot

NoC-Based Thread Synchronization in a Custom Manycore System

inferred← citeshttps://doi.org/10.1007/978-3-319-70010-6_26openalex-snapshot

An Automated Image-Based Approach for Tracking Pedestrian Movements from Top-View Video

inferred← citeshttps://doi.org/10.1007/978-3-319-70090-8_6openalex-snapshot

Object Tracking Based on Mean Shift Algorithm and Kernelized Correlation Filter Algorithm

inferred← citeshttps://doi.org/10.1007/978-3-319-71607-7_17openalex-snapshot

Online Fast Deep Learning Tracker Based on Deep Sparse Neural Networks

inferred← citeshttps://doi.org/10.1007/978-3-319-73447-7_37openalex-snapshot

A Virtual Channel Allocation Algorithm for NoC

inferred← citeshttps://doi.org/10.1007/978-3-319-73697-6_14openalex-snapshot

Sketch-Based Modeling and Immersive Display Techniques for Indoor Crime Scene Presentation

inferred← citeshttps://doi.org/10.1007/978-3-319-77610-1_9openalex-snapshot

Lightweight Hardware Synchronization for Avoiding Buffer Overflows in Network-on-Chips

inferred← citeshttps://doi.org/10.1007/978-3-319-91152-6_25openalex-snapshot

A Framework for Interactive Exploratory Learning Analytics

inferred← citeshttps://doi.org/10.1007/978-3-319-95098-3_26openalex-snapshot

Asymmetry Degree as a Tool for Comparing Interestingness Measures in Decision Making: The Case of Bayesian Confirmation Measures

inferred← citeshttps://doi.org/10.1007/978-3-319-95678-7_13openalex-snapshot

“Hands-on-Remote” Laboratories

inferred← citeshttps://doi.org/10.1007/978-3-540-69384-0_30openalex-snapshot

A2DLT: Divisible Load Balancing Model for Scheduling Communication-Intensive Grid Applications

inferred← citeshttps://doi.org/10.1007/978-3-540-69384-0_48openalex-snapshot

Heuristics Core Mapping in On-Chip Networks for Parallel Stream-Based Applications

inferred← citeshttps://doi.org/10.1007/978-3-540-71431-6_5openalex-snapshot

Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs

inferred← citeshttps://doi.org/10.1007/978-3-540-71431-6_6openalex-snapshot

Systematic Customization of On-Chip Crossbar Interconnects

inferred← citeshttps://doi.org/10.1007/978-3-540-71496-5_35openalex-snapshot

Entropy-Based Authorship Search in Large Document Collections

inferred← citeshttps://doi.org/10.1007/978-3-540-72584-8_59openalex-snapshot

Adaptive Divisible Load Model for Scheduling Data-Intensive Grid Applications

inferred← citeshttps://doi.org/10.1007/978-3-540-72685-2_23openalex-snapshot

Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips

inferred← citeshttps://doi.org/10.1007/978-3-540-74309-5_21openalex-snapshot

Power Consumption and Performance Analysis of 3D NoCs

inferred← citeshttps://doi.org/10.1007/978-3-540-74442-9_1openalex-snapshot

System-Level Application-Specific NoC Design for Network and Multimedia Applications

inferred← citeshttps://doi.org/10.1007/978-3-540-74472-6_61openalex-snapshot

An Integrated Approach for Scheduling Divisible Load on Large Scale Data Grids

inferred← citeshttps://doi.org/10.1007/978-3-540-74742-0_30openalex-snapshot

A Distributed Hebb Neural Network for Network Anomaly Detection

inferred← citeshttps://doi.org/10.1007/978-3-540-74742-0_77openalex-snapshot

Design and Analysis of Multicast Communication in Multidimensional Mesh Networks

inferred← citeshttps://doi.org/10.1007/978-3-540-74784-0_7openalex-snapshot

A Dynamic Adjustment Strategy for File Transformation in Data Grids

inferred← citeshttps://doi.org/10.1007/978-3-540-75530-2_13openalex-snapshot

Compact Set Representation for Information Retrieval

inferred← citeshttps://doi.org/10.1007/978-3-540-76837-1_43openalex-snapshot

rHALB: A New Load-Balanced Routing Algorithm for k-ary n-cube Networks

inferred← citeshttps://doi.org/10.1007/978-3-540-78610-8_31openalex-snapshot

Stream Transfer Balancing Scheme Utilizing Multi-path Routing in Networks on Chip

inferred← citeshttps://doi.org/10.1007/978-3-540-79187-4_23openalex-snapshot

Two O(n 2)Time Fault–Tolerant Parallel Algorithm for Inter NoC Communication in NiP

inferred← citeshttps://doi.org/10.1007/978-3-540-85857-7_7openalex-snapshot

A Hardware-Software Design Framework for Distributed Cellular Computing

inferred← citeshttps://doi.org/10.1007/978-3-540-89437-7_1openalex-snapshot

Engineering of Software-Intensive Systems: State of the Art and Research Challenges

inferred← citeshttps://doi.org/10.1007/978-3-540-89985-3_84openalex-snapshot

Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability

inferred← citeshttps://doi.org/10.1007/978-3-540-92990-1_27openalex-snapshot

In-Network Caching for Chip Multiprocessors

inferred← citeshttps://doi.org/10.1007/978-3-540-95885-7_23openalex-snapshot

Applications of Page Ranking in P Systems

inferred← citeshttps://doi.org/10.1007/978-3-642-01970-8_17openalex-snapshot

New Optimal Load Allocation for Scheduling Divisible Data Grid Applications

inferred← citeshttps://doi.org/10.1007/978-3-642-02345-3_21openalex-snapshot

Lossless and Near-Lossless Image Compression Scheme Utilizing Blending-Prediction-Based Approach

inferred← citeshttps://doi.org/10.1007/978-3-642-02611-9_48openalex-snapshot

Towards Communicative Face Occlusions: Machine Detection of Hand-over-Face Gestures

inferred← citeshttps://doi.org/10.1007/978-3-642-04394-9_58openalex-snapshot

A Fuzzy Approach for Studying Combinatorial Regulatory Actions of Transcription Factors in Yeast

inferred← citeshttps://doi.org/10.1007/978-3-642-10520-3_105openalex-snapshot

Comparison of Optimisation Algorithms for Deformable Template Matching

inferred← citeshttps://doi.org/10.1007/978-3-642-11568-4_10openalex-snapshot

Moving Object Detection and Tracking in Forward Looking Infra-Red Aerial Imagery

inferred← citeshttps://doi.org/10.1007/978-3-642-11756-5_2openalex-snapshot

Recognizing Interactions in Video

inferred← citeshttps://doi.org/10.1007/978-3-642-12275-0_28openalex-snapshot

XML Retrieval Using Pruned Element-Index Files

inferred← citeshttps://doi.org/10.1007/978-3-642-13059-5_51openalex-snapshot

Evaluation of Rare Event Detection

inferred← citeshttps://doi.org/10.1007/978-3-642-13119-6_14openalex-snapshot

Network-on-Chip Routing Algorithms by Breaking Cycles

inferred← citeshttps://doi.org/10.1007/978-3-642-15390-7_47openalex-snapshot

Human Tracking: A State-of-Art Survey

inferred← citeshttps://doi.org/10.1007/978-3-642-15781-3_17openalex-snapshot

Top-k Ranked Document Search in General Text Databases

inferred← citeshttps://doi.org/10.1007/978-3-642-17277-9_13openalex-snapshot

An Improved Shape Matching Algorithm for Deformable Objects Using a Global Image Feature

inferred← citeshttps://doi.org/10.1007/978-3-642-19137-4_19openalex-snapshot

An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation

inferred← citeshttps://doi.org/10.1007/978-3-642-19315-6_23openalex-snapshot

Analytical Dynamic Programming Tracker

inferred← citeshttps://doi.org/10.1007/978-3-642-20986-4_10openalex-snapshot

A New Approach to Network Optimization Using Chaos-Genetic Algorithm

inferred← citeshttps://doi.org/10.1007/978-3-642-21153-9_26openalex-snapshot

Job Scheduling for Dynamic Data Replication Strategy based on Federation Data Grid Systems

inferred← citeshttps://doi.org/10.1007/978-3-642-21593-3_39openalex-snapshot

Maneuvering Head Motion Tracking by Coarse-to-Fine Particle Filter

inferred← citeshttps://doi.org/10.1007/978-3-642-22185-9_9openalex-snapshot

Improved-XY: A High Performance Wormhole-Switched Routing Algorithm for Irregular 2-D Mesh NoC

inferred← citeshttps://doi.org/10.1007/978-3-642-22191-0_43openalex-snapshot

Mining Interesting Association Rules of Student Suffering Mathematics Anxiety

inferred← citeshttps://doi.org/10.1007/978-3-642-23178-0_37openalex-snapshot

Virtual Path Implementation of Multi-stream Routing in Network on Chip

inferred← citeshttps://doi.org/10.1007/978-3-642-24658-6_13openalex-snapshot

Skalierbare Rechensysteme für Echtzeitanwendungen

inferred← citeshttps://doi.org/10.1007/978-3-642-25899-2_102openalex-snapshot

Quadrature Kalman Probability Hypothesis Density Filter for Multi-Target Tracking

inferred← citeshttps://doi.org/10.1007/978-3-642-27287-5_19openalex-snapshot

Research of Distributed Index Based on Lucene

inferred← citeshttps://doi.org/10.1007/978-3-642-28293-5_20openalex-snapshot

Streamlined Network-on-Chip for Multicore Embedded Architectures

inferred← citeshttps://doi.org/10.1007/978-3-642-28365-9_33openalex-snapshot

R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip

inferred← citeshttps://doi.org/10.1007/978-3-642-28661-2_8openalex-snapshot

Simultaneous Detection and Tracking with Multiple Cameras

inferred← citeshttps://doi.org/10.1007/978-3-642-28783-1_5openalex-snapshot

A Context-Based Surveillance Framework for Large Infrastructures

inferred← citeshttps://doi.org/10.1007/978-3-642-28977-4_3openalex-snapshot

Vision Based Semantic Analysis of Surveillance Videos

inferred← citeshttps://doi.org/10.1007/978-3-642-29157-9_38openalex-snapshot

Algorithm Research of Top-Down Mining Maximal Frequent SubGraph Based on Tree Structure

inferred← citeshttps://doi.org/10.1007/978-3-642-30232-9_12openalex-snapshot

Review of the Application of Matrix Information Theory in Video Surveillance

inferred← citeshttps://doi.org/10.1007/978-3-642-31513-8_76openalex-snapshot

Human Tracking in Video Surveillance

inferred← citeshttps://doi.org/10.1007/978-3-642-31561-9_12openalex-snapshot

Brain Memory Inspired Template Updating Modeling for Robust Moving Object Tracking Using Particle Filter

inferred← citeshttps://doi.org/10.1007/978-3-642-32281-5_8openalex-snapshot

A High-Performance Algorithm for Frequent Itemset Mining

inferred← citeshttps://doi.org/10.1007/978-3-642-32584-7_17openalex-snapshot

A Fast Algorithm for Frequent Itemset Mining Using Patricia* Structures

inferred← citeshttps://doi.org/10.1007/978-3-642-32597-7_36openalex-snapshot

Evaluating Skyline Queries on Spatial Web Objects

inferred← citeshttps://doi.org/10.1007/978-3-642-32600-4_34openalex-snapshot

Mining Frequent Itemsets Using Node-Sets of a Prefix-Tree

inferred← citeshttps://doi.org/10.1007/978-3-642-32615-8_61openalex-snapshot

Bio-inspired Visual Information Processing – The Neuromorphic Approach

inferred← citeshttps://doi.org/10.1007/978-3-642-33140-4_5openalex-snapshot

DSP Embedded Smart Surveillance Sensor with Robust SWAD-Based Tracker

inferred← citeshttps://doi.org/10.1007/978-3-642-33460-3_29openalex-snapshot

An Efficiently Computable Support Measure for Frequent Subgraph Pattern Mining

inferred← citeshttps://doi.org/10.1007/978-3-642-33805-2_29openalex-snapshot

Pedestrian Detection by Neuromorphic Visual Information Processing

inferred← citeshttps://doi.org/10.1007/978-3-642-34595-1_8openalex-snapshot

Improved HSV-Based Gaussian Mixture Modeling for Moving Foreground Segmentation

inferred← citeshttps://doi.org/10.1007/978-3-642-34732-0_18openalex-snapshot

Combinatorial Properties of 2D Discrete Rigid Transformations under Pixel-Invariance Constraints

inferred← citeshttps://doi.org/10.1007/978-3-642-35455-7_2openalex-snapshot

Mining Frequent Common Families in Trees

inferred← citeshttps://doi.org/10.1007/978-3-642-35864-7_55openalex-snapshot

Intelligent Robust Router

inferred← citeshttps://doi.org/10.1007/978-3-642-37067-0_14openalex-snapshot

Sufficient Conditions for Topological Invariance of 2D Images under Rigid Transformations

inferred← citeshttps://doi.org/10.1007/978-3-642-37149-3_22openalex-snapshot

A Novel Moving Objects Detection Model Based on Images Registration within Sliding Time Windows

inferred← citeshttps://doi.org/10.1007/978-3-642-37371-8_32openalex-snapshot

Ten-LoPP: Tensor Locality Preserving Projections Approach for Moving Object Detection and Tracking

inferred← citeshttps://doi.org/10.1007/978-3-642-37484-5_30openalex-snapshot

A Robust Particle Tracker via Markov Chain Monte Carlo Posterior Sampling

inferred← citeshttps://doi.org/10.1007/978-3-642-37832-4_27openalex-snapshot

An Application of Soft Computing Techniques to Track Moving Objects in Video Sequences

inferred← citeshttps://doi.org/10.1007/978-3-642-39342-6_27openalex-snapshot

Kernel Fuzzy Similarity Measure-Based Spectral Clustering for Image Segmentation

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