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High Level Synthesis of Timed Asynchronous Circuits

https://doi.org/10.1109/async.2005.22
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-3636-9openalex-snapshot
High — Level Synthesis
inferredcites →https://doi.org/10.1093/comjnl/45.1.12openalex-snapshot
Balsa: An Asynchronous Hardware Synthesis Language
inferredcites →https://doi.org/10.1109/async.2000.836975openalex-snapshot
High-level asynchronous system design using the ACK framework
inferredcites →https://doi.org/10.1109/async.2000.836976openalex-snapshot
Automatic process-oriented control circuit generation for asynchronous high-level synthesis
inferredcites →https://doi.org/10.1109/async.2004.1299294openalex-snapshot
A general purpose behavioural asynchronous synthesis system
inferredcites →https://doi.org/10.1109/async.2004.1299295openalex-snapshot
Synthesis of speed independent circuits based on decomposition
inferredcites →https://doi.org/10.1109/csd.2004.1309112openalex-snapshot
Logic synthesis for asynchronous circuits based on Petri net unfoldings and incremental SAT
inferredcites →https://doi.org/10.1109/dac.2003.1219060openalex-snapshot
High-level synthesis of asynchronous systems by data-driven decomposition
inferredcites →https://doi.org/10.1109/edac.1993.386498openalex-snapshot
High-level synthesis of asynchronous systems: Scheduling and process synchronization
inferredcites →https://doi.org/10.1109/iccad.2003.159771openalex-snapshot
ILP models for the synthesis of asynchronous control circuits
inferredcites →https://doi.org/10.1109/iccd.1999.808566openalex-snapshot
Architectural synthesis of timed asynchronous systems
inferredcites →https://doi.org/10.1109/icvd.2003.1183177openalex-snapshot
SPARK: a high-level synthesis framework for applying parallelizing compiler transformations
inferredcites →https://doi.org/10.1109/iscas.2003.1206232openalex-snapshot
A zero-time-overhead asynchronous four-phase controller
inferredcites →https://doi.org/10.1109/tcad.2006.883912openalex-snapshot
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
inferredcites →https://doi.org/10.1109/tcad.2006.888269openalex-snapshot
Synthesis of Timed Circuits Based on Decomposition
inferredcites →https://doi.org/10.1145/775832.775962openalex-snapshot
High-level synthesis of asynchronous systems by data-driven decomposition
inferredcites →https://doi.org/10.25405/ncl.34276650openalex-snapshot
Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers
inferredcites →https://doi.org/10.5555/996070.1009982openalex-snapshot
ILP Models for the Synthesis of Asynchronous Control Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/11901914_19openalex-snapshot
Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis
inferred← citeshttps://doi.org/10.1007/s13369-020-04541-3openalex-snapshot
Novel Asynchronous Pipeline Architectures for High-Throughput Applications
inferred← citeshttps://doi.org/10.1016/j.vlsi.2019.12.001openalex-snapshot
A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding
inferred← citeshttps://doi.org/10.1017/cbo9780511674730openalex-snapshot
A Designer's Guide to Asynchronous VLSI
inferred← citeshttps://doi.org/10.1109/acsd.2008.4574589openalex-snapshot
Using edge-triggering in the asynchronous synthesis of write-after-read operations
inferred← citeshttps://doi.org/10.1109/acsd.2008.4574603openalex-snapshot
Asynchronous pipeline controller based on early acknowledgement protocol
inferred← citeshttps://doi.org/10.1109/async.2012.29openalex-snapshot
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits
inferred← citeshttps://doi.org/10.1109/async.2016.11openalex-snapshot
Optimising Bundled-Data Balsa Circuits
inferred← citeshttps://doi.org/10.1109/async48570.2021.00009openalex-snapshot
Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures
inferred← citeshttps://doi.org/10.1109/dsd.2014.98openalex-snapshot
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA
inferred← citeshttps://doi.org/10.1109/icaecc.2014.7002414openalex-snapshot
On the design of hazard free reversible asynchronous circuits
inferred← citeshttps://doi.org/10.1109/iccad.2017.8203806openalex-snapshot
Data path optimisation and delay matching for asynchronous bundled-data balsa circuits
inferred← citeshttps://doi.org/10.1109/intercon.2016.7815571openalex-snapshot
Synthesis of bundled–data asynchronous pipelines with reduced matched delays on FPGAS
inferred← citeshttps://doi.org/10.1109/tcad.2005.854638openalex-snapshot
Verification of timed circuits with failure-directed abstractions
inferred← citeshttps://doi.org/10.1109/tcad.2006.888269openalex-snapshot
Synthesis of Timed Circuits Based on Decomposition
inferred← citeshttps://doi.org/10.1587/transinf.e93.d.2145openalex-snapshot
Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol
inferred← citeshttps://doi.org/10.3233/fi-2009-141openalex-snapshot
Application of Concurrency in the Asynchronous Design of Write-after-read Operations
inferred← citeshttps://doi.org/10.32657/10356/47034openalex-snapshot
Design methodologies for low-power asynchronous-logic digital systems
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