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A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4612-4476-9_35openalex-snapshot
The Limitations to Delay-Insensitivity in Asynchronous Circuits
inferredcites →https://doi.org/10.1109/43.980253openalex-snapshot
Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions
inferredcites →https://doi.org/10.1109/5.740025openalex-snapshot
Min-max timing analysis and an application to asynchronous circuits
inferredcites →https://doi.org/10.1109/aspdac.2001.913347openalex-snapshot
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits
inferredcites →https://doi.org/10.1109/async.2000.836983openalex-snapshot
Asynchronous design using commercial HDL synthesis tools
inferredcites →https://doi.org/10.1109/async.2001.914082openalex-snapshot
Designing fast asynchronous circuits
inferredcites →https://doi.org/10.1109/async.2005.22openalex-snapshot
High Level Synthesis of Timed Asynchronous Circuits
inferredcites →https://doi.org/10.1109/async.2009.27openalex-snapshot
A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits
inferredcites →https://doi.org/10.1109/async.2009.31openalex-snapshot
Heuristic Based throughput Analysis and Optimization of Asynchronous Pipelines
inferredcites →https://doi.org/10.1109/async.2011.13openalex-snapshot
CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits
inferredcites →https://doi.org/10.1109/date.2010.5457239openalex-snapshot
A fully-asynchronous low-power framework for GALS NoC integration
inferredcites →https://doi.org/10.1109/date.2011.5763222openalex-snapshot
Redressing timing issues for speed-independent circuits in deep submicron age
inferredcites →https://doi.org/10.1109/iccd.2009.5413183openalex-snapshot
Automatic synthesis of computation interference constraints for relative timing verification
inferredcites →https://doi.org/10.1109/mdt.2002.1018139openalex-snapshot
Design of asynchronous circuits using synchronous CAD tools
inferredcites →https://doi.org/10.1109/mdt.2011.114openalex-snapshot
Proteus: An ASIC Flow for GHz Asynchronous Designs
inferredcites →https://doi.org/10.1109/wcadm.1995.514647openalex-snapshot
Stretching quasi delay insensitivity by means of extended isochronic forks
inferredcites →https://doi.org/10.1145/1228784.1228858openalex-snapshot
Using standard asic back-end for qdi asynchronous circuits
inferredcites →https://doi.org/10.1145/370155.370450openalex-snapshot
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits
inferredcites →https://doi.org/10.21236/ada447737openalex-snapshot
The Limitations to Delay-Insensitivity in Asynchronous Circuits
inferredcites →https://doi.org/10.5555/1870926.1870938openalex-snapshot
A fully-asynchronous low-power framework for GALS NoC integration
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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The fast evolving landscape of on-chip communication
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Low power sub‐threshold asynchronous quasi‐delay‐insensitive 32‐bit arithmetic and logic unit based on autonomous signal‐validity half‐buffer
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Reconditioning: Automatic Power Optimization of QDI Circuits
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Timing Driven Placement for Quasi Delay-Insensitive Circuits
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Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation
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Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow
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Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone
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Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools
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LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell Libraries
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Asynchronous circuit placement by Lagrangian relaxation
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Descriptor: Asynchronous Circuit Logic Dataset (ACLD)
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High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits
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Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack
inferred← citeshttps://doi.org/10.1109/isqed.2014.6783394openalex-snapshot
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design
inferred← citeshttps://doi.org/10.1109/jssc.2014.2317137openalex-snapshot
A Fine-Grain Variation-Aware Dynamic ${\rm Vdd}$ -Hopping AVFS Architecture on a 32 nm GALS MPSoC
inferred← citeshttps://doi.org/10.1109/jssc.2016.2611497openalex-snapshot
A $4 \times 4 \times 2$ Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
inferred← citeshttps://doi.org/10.1109/mssc.2016.2573864openalex-snapshot
Asynchronous Circuit Designs for the Internet of Everything: A Methodology for Ultralow-Power Circuits with GALS Architecture
inferred← citeshttps://doi.org/10.1109/ngcas.2017.49openalex-snapshot
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/sbcci55532.2022.9893258openalex-snapshot
Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design
inferred← citeshttps://doi.org/10.1109/sbcci60457.2023.10261656openalex-snapshot
Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V
inferred← citeshttps://doi.org/10.1109/tcad.2016.2571840openalex-snapshot
Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits
inferred← citeshttps://doi.org/10.1109/tcad.2017.2697947openalex-snapshot
Two Approaches for Timing-Driven Placement by Lagrangian Relaxation
inferred← citeshttps://doi.org/10.1109/tcsi.2017.2772206openalex-snapshot
NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization
inferred← citeshttps://doi.org/10.1109/tvlsi.2026.3716692openalex-snapshot
HyPA : A Low-Latency Hybrid Pipeline Asynchronous Router for Network-on-Chip Architectures in GALS-Based SoCs
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2014.7004164openalex-snapshot
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study
inferred← citeshttps://doi.org/10.1109/vlsi-soc46417.2020.9344096openalex-snapshot
Automatic Timing Closure for Relative Timed Designs
inferred← citeshttps://doi.org/10.1145/2660540.2660984openalex-snapshot
Automated Synthesis of Cell Libraries for Asynchronous Circuits
inferred← citeshttps://doi.org/10.26053/0h-ezbd-9r00openalex-snapshot
Achieving backend robustness for timed asynchronous circuits
inferred← citeshttps://doi.org/10.29292/jics.v16i2.518openalex-snapshot
Robust and Energy-Efficient Hardware: The Case for Asynchronous Design
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Asynchronous Circuit Principles and a Survey of Associated Design Tools
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Components to Support Choice in Self-Timed Asynchronous Design Flows
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Machine learning based automated evaluation of piping design
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Low Normalized Energy Derivation Asynchronous Circuit Synthesis Flow through Fork-Join Slack Matching for Cryptographic Applications
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Simultaneous Slack Matching, Gate Sizing and Repeater Insertion for Asynchronous Circuits
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Asynchronous interface circuit for nonlinear connectivity in multicore spiking neural networks
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Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools
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Asynchronous circuit placement by lagrangian relaxation
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Logical equivalence checking of asynchronous circuits using commercial tools
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