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Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters

https://doi.org/10.1109/async.2015.24
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/9780470517147openalex-snapshot
Synchronization and Arbitration in Digital Systems
inferredcites →https://doi.org/10.1016/j.vlsi.2008.03.001openalex-snapshot
QNoC asynchronous router
inferredcites →https://doi.org/10.1109/4.766818openalex-snapshot
Beware the three-way arbiter
inferredcites →https://doi.org/10.1109/92.311648openalex-snapshot
A low latency asynchronous arbitration circuit
inferredcites →https://doi.org/10.1109/92.544412openalex-snapshot
CMOS design of the tree arbiter element
inferredcites →https://doi.org/10.1109/async.2000.836990openalex-snapshot
Priority arbiters
inferredcites →https://doi.org/10.1109/async.2011.20openalex-snapshot
Address-Event Communication Using Token-Ring Mutual Exclusion
inferredcites →https://doi.org/10.1109/date.2010.5457239openalex-snapshot
A fully-asynchronous low-power framework for GALS NoC integration
inferredcites →https://doi.org/10.1109/mdt.2007.150openalex-snapshot
A Highly Scalable GALS Crossbar Using Token Ring Arbitration
inferredcites →https://doi.org/10.1109/mdt.2011.113openalex-snapshot
Metastability and Synchronizers: A Tutorial
inferredcites →https://doi.org/10.3233/fi-2011-414openalex-snapshot
Flat Arbiters
inferredcites →https://doi.org/10.5555/1870926.1870938openalex-snapshot
A fully-asynchronous low-power framework for GALS NoC integration
inferredcites →https://doi.org/10.5555/2616606.2617035openalex-snapshot
A tree arbiter cell for high speed resource sharing in asynchronous environments
inferredcites →https://doi.org/10.7873/date.2013.079openalex-snapshot
A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems
inferredcites →https://doi.org/10.7873/date.2014.308openalex-snapshot
A tree arbiter cell for high speed resource sharing in asynchronous environments
inferredcites →https://doi.org/10.7907/b2dbm-s0762openalex-snapshot
The Design of a Self-timed Circuit for Distributed Mutual Exclusion

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-4-431-56594-9_9openalex-snapshot
Responsiveness and Timing
inferred← citeshttps://doi.org/10.1007/s00521-016-2571-6openalex-snapshot
Artificial neural networks based dynamic priority arbitration for asynchronous flow control
inferred← citeshttps://doi.org/10.1109/aicas54282.2022.9869944openalex-snapshot
An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing
inferred← citeshttps://doi.org/10.1109/async.2017.21openalex-snapshot
A High-Throughput Asynchronous Multi-resource Arbiter Using a Pipelined Assignment Approach
inferred← citeshttps://doi.org/10.1109/async65240.2025.00013openalex-snapshot
A Synthesis Toolflow for the Predictable Implementation of High-Performance Bundled-Data Asynchronous NoCs on FPGA
inferred← citeshttps://doi.org/10.1109/async69614.2026.00015openalex-snapshot
A Test Architecture for Bundled-Data Asynchronous NoC Switches Using Commercial ATPG Tools
inferred← citeshttps://doi.org/10.1109/icsict62049.2024.10830960openalex-snapshot
Asynchronous Arbitration Circuit Optimization for Multicore Neuromorphic Processors
inferred← citeshttps://doi.org/10.1109/istm62799.2024.10931582openalex-snapshot
Time-Domain Argmax Architecture for the Tsetlin Machine Classification
inferred← citeshttps://doi.org/10.1109/mm.2020.3002790openalex-snapshot
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems
inferred← citeshttps://doi.org/10.1109/newcas49341.2020.9159757openalex-snapshot
Design and Comparison of Synthesizable Fair Asynchronous Arbiter
inferred← citeshttps://doi.org/10.1109/newcas58973.2024.10666312openalex-snapshot
An Asynchronous Winner-Takes-All Arbitration Architecture for Tsetlin Machine Acceleration
inferred← citeshttps://doi.org/10.1109/ngcas.2017.49openalex-snapshot
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/nocs.2016.7579330openalex-snapshot
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs
inferred← citeshttps://doi.org/10.1145/3822454.3822495openalex-snapshot
Cross-Layer Analysis of Permanent Faults in Asynchronous NoCs for Neuromorphic Computing
inferred← citeshttps://doi.org/10.1587/elex.19.20220265openalex-snapshot
Design of low latency asynchronous arbiter based on standard cell library
inferred← citeshttps://doi.org/10.3390/s21123949openalex-snapshot
Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout
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