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Qualifying Relative Timing Constraints for Asynchronous Circuits

https://doi.org/10.1109/async.2016.23
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1017/cbo9780511674730openalex-snapshot
A Designer's Guide to Asynchronous VLSI
inferredcites →https://doi.org/10.1109/4.902762openalex-snapshot
An asynchronous instruction length decoder
inferredcites →https://doi.org/10.1109/43.293952openalex-snapshot
Analysis of cyclic combinational circuits
inferredcites →https://doi.org/10.1109/async.2002.1000302openalex-snapshot
Relative timing based verification of timed circuits and systems
inferredcites →https://doi.org/10.1109/async.2009.26openalex-snapshot
Characterization of Asynchronous Templates for Integration into Clocked CAD Flows
inferredcites →https://doi.org/10.1109/cicc.1993.590682openalex-snapshot
Delay and area optimization for discrete gate sizes under double-sided timing constraints
inferredcites →https://doi.org/10.1109/iccd.2009.5413183openalex-snapshot
Automatic synthesis of computation interference constraints for relative timing verification
inferredcites →https://doi.org/10.1109/tvlsi.2002.801606openalex-snapshot
Relative timing [asynchronous design]
inferredcites →https://doi.org/10.1109/vlsid.2016.111openalex-snapshot
Path Based Timing Validation for Timed Asynchronous Design
inferredcites →https://doi.org/10.5555/2485288.2485349openalex-snapshot
Design of low energy, high performance synchronous and asynchronous 64-point FFT
inferredcites →https://doi.org/10.7873/date.2013.062openalex-snapshot
Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT
inferredcites →https://doi.org/10.7907/z92v2d4zopenalex-snapshot
Pipelined Asynchronous Circuits

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-81641-4_7openalex-snapshot
Learning Based Timing Closure on Relative Timed Design
inferred← citeshttps://doi.org/10.1049/cdt2.12032openalex-snapshot
Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow
inferred← citeshttps://doi.org/10.1109/access.2023.3326856openalex-snapshot
HPSAP: A High-Performance and Synthesizable Asynchronous Pipeline With Quasi-2phase Conversion Method
inferred← citeshttps://doi.org/10.1109/async.2017.22openalex-snapshot
Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow
inferred← citeshttps://doi.org/10.1109/async.2018.00036openalex-snapshot
Static Timing Analysis of Asynchronous Bundled-Data Circuits
inferred← citeshttps://doi.org/10.1109/async49171.2020.00010openalex-snapshot
Cyclone: A Static Timing and Power Engine for Asynchronous Circuits
inferred← citeshttps://doi.org/10.1109/cicn49253.2020.9242604openalex-snapshot
Effective Data Transmission with UART on Kintex-7 FPGA
inferred← citeshttps://doi.org/10.1109/tcad.2020.3038337openalex-snapshot
A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools
inferred← citeshttps://doi.org/10.1109/tcsi.2020.3036011openalex-snapshot
An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling
inferred← citeshttps://doi.org/10.1109/tcsii.2021.3100524openalex-snapshot
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method
inferred← citeshttps://doi.org/10.1109/vlsi-soc46417.2020.9344096openalex-snapshot
Automatic Timing Closure for Relative Timed Designs
inferred← citeshttps://doi.org/10.70675/67615de8zf950z4d02z9dd1z33698f6bb4ffopenalex-snapshot
Concevoir des circuits sécurisés à très faible consommation : une alternative basée sur l’asynchrone
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