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Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s11265-015-1070-9openalex-snapshot
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision
inferredcites →https://doi.org/10.1109/async.2009.26openalex-snapshot
Characterization of Asynchronous Templates for Integration into Clocked CAD Flows
inferredcites →https://doi.org/10.1109/async.2012.29openalex-snapshot
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits
inferredcites →https://doi.org/10.1109/async.2016.23openalex-snapshot
Qualifying Relative Timing Constraints for Asynchronous Circuits
inferredcites →https://doi.org/10.1109/date.2010.5457239openalex-snapshot
A fully-asynchronous low-power framework for GALS NoC integration
inferredcites →https://doi.org/10.1109/dsd.2015.104openalex-snapshot
A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework
inferredcites →https://doi.org/10.1109/jssc.2014.2369508openalex-snapshot
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS
inferredcites →https://doi.org/10.1109/lascas.2015.7250461openalex-snapshot
BAT-Hermes: A transition-signaling bundled-data NoC router
inferredcites →https://doi.org/10.1109/mcas.2004.1330747openalex-snapshot
Feature - Xpipes : a network-on-chip architecture for gigascale systems-on-chip
inferredcites →https://doi.org/10.1109/mdat.2015.2413759openalex-snapshot
Asynchronous Design—Part 1: Overview and Recent Advances
inferredcites →https://doi.org/10.1109/mdt.2011.114openalex-snapshot
Proteus: An ASIC Flow for GHz Asynchronous Designs
inferredcites →https://doi.org/10.1109/mm.2002.1044296openalex-snapshot
Chain: a delay-insensitive chip area interconnect
inferredcites →https://doi.org/10.1109/mm.2004.1268991openalex-snapshot
Asynchronous interconnect for synchronous soc design
inferredcites →https://doi.org/10.1109/nocs.2014.7008774openalex-snapshot
A loosely synchronizing asynchronous router for TDM-scheduled NOCs
inferredcites →https://doi.org/10.1109/nocs.2016.7579330openalex-snapshot
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs
inferredcites →https://doi.org/10.1109/norchip.2014.7004742openalex-snapshot
Synthesis and layout of an asynchronous network-on-chip using Standard EDA tools
inferredcites →https://doi.org/10.1109/tc.2012.142openalex-snapshot
Overview of the SpiNNaker System Architecture
inferredcites →https://doi.org/10.1109/tcad.2011.2149870openalex-snapshot
Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs
inferredcites →https://doi.org/10.1109/tvlsi.2007.898732openalex-snapshot
MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines
inferredcites →https://doi.org/10.1109/vlsid.2016.111openalex-snapshot
Path Based Timing Validation for Timed Asynchronous Design
inferredcites →https://doi.org/10.13140/rg.2.2.14678.04169openalex-snapshot
Relative Placement in Timed Asynchronous Design
inferredcites →https://doi.org/10.23919/date.2017.7927084openalex-snapshot
An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart
inferredcites →https://doi.org/10.5555/1870926.1870938openalex-snapshot
A fully-asynchronous low-power framework for GALS NoC integration
inferredcites →https://doi.org/10.7873/date.2013.079openalex-snapshot
A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/access.2023.3326856openalex-snapshot
HPSAP: A High-Performance and Synthesizable Asynchronous Pipeline With Quasi-2phase Conversion Method
inferred← citeshttps://doi.org/10.1109/aicas54282.2022.9869944openalex-snapshot
An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing
inferred← citeshttps://doi.org/10.1109/async49171.2020.00010openalex-snapshot
Cyclone: A Static Timing and Power Engine for Asynchronous Circuits
inferred← citeshttps://doi.org/10.1109/async58294.2023.10239566openalex-snapshot
Yak: An Asynchronous Bundled Data Pipeline Description Language
inferred← citeshttps://doi.org/10.1109/async58294.2023.10239574openalex-snapshot
Core Interface Optimization for Multi-core Neuromorphic Processors
inferred← citeshttps://doi.org/10.1109/host55118.2023.10133813openalex-snapshot
Low-Latency Masking with Arbitrary Protection Order Based on Click Elements
inferred← citeshttps://doi.org/10.1109/jproc.2023.3273520openalex-snapshot
Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial Intelligence
inferred← citeshttps://doi.org/10.1109/mm.2020.3002790openalex-snapshot
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems
inferred← citeshttps://doi.org/10.1109/ngcas.2017.49openalex-snapshot
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tcad.2020.3038337openalex-snapshot
A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools
inferred← citeshttps://doi.org/10.1109/tvlsi.2024.3418769openalex-snapshot
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint
inferred← citeshttps://doi.org/10.1109/vlsi-soc46417.2020.9344096openalex-snapshot
Automatic Timing Closure for Relative Timed Designs
inferred← citeshttps://doi.org/10.23919/date58400.2024.10546503openalex-snapshot
An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint
inferred← citeshttps://doi.org/10.3390/electronics10151821openalex-snapshot
Double-Layer Energy Efficient Synchronous-Asynchronous Circuit-Switched NoC
inferred← citeshttps://doi.org/10.5167/uzh-217499openalex-snapshot
Bottom-Up and Top-Down Neural Processing Systems Design: Neuromorphic Intelligence as the Convergence of Natural and Artificial Intelligence
inferred← citeshttps://doi.org/10.70675/6dddcaa3za5d1z49b0zb410z15780f80f236openalex-snapshot
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