On the public citation graph
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software
0 signed · 63 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4615-5107-2openalex-snapshot
Memory Issues in Embedded Systems-on-Chip
inferredcites →https://doi.org/10.1007/978-3-540-30113-4_14openalex-snapshot
Integrated Intra- and Inter-task Cache Analysis for Preemptive Multi-tasking Real-Time Systems
inferredcites →https://doi.org/10.1023/a:1008119029962openalex-snapshot
Guest Editorial: A Review of Worst-Case Execution-Time Analysis
inferredcites →https://doi.org/10.1023/a:1008141130870openalex-snapshot
Fast and Precise WCET Prediction by Separated Cache and Path Analyses
inferredcites →https://doi.org/10.1109/40.464580openalex-snapshot
Embedded control problems, Thumb, and the ARM7TDMI
inferredcites →https://doi.org/10.1109/codes.2002.1003604openalex-snapshot
Scratchpad memory: a design alternative for cache on-chip memory in embedded systems
inferredcites →https://doi.org/10.1109/date.2002.998306openalex-snapshot
Assigning program and data objects to scratchpad for energy reduction
inferredcites →https://doi.org/10.1109/iccad.1995.480144openalex-snapshot
Performance estimation of embedded software with instruction cache modeling
inferredcites →https://doi.org/10.1109/jproc.2003.814618openalex-snapshot
The influence of processor architecture on the design and the results of WCET tools
inferredcites →https://doi.org/10.1109/real.1996.563722openalex-snapshot
Cache modeling for real-time software: beyond direct mapped instruction caches
inferredcites →https://doi.org/10.1145/1016720.1016748openalex-snapshot
Dynamic overlay of scratchpad memory for energy minimization
inferredcites →https://doi.org/10.1145/309847.309902openalex-snapshot
Memory exploration for low power, embedded systems
inferredcites →https://doi.org/10.1145/378239.379049openalex-snapshot
Dynamic management of scratch-pad memory space
inferredcites →https://doi.org/10.1145/581199.581247openalex-snapshot
Reducing energy consumption by dynamic copying of instructions onto onchip memory
inferredcites →https://doi.org/10.5555/224841.225068openalex-snapshot
Performance estimation of embedded software with instruction cache modeling
inferredcites →https://doi.org/10.5555/882452.874376openalex-snapshot
Assigning Program and Data Objects to Scratchpad for Energy Reduction
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-32700-1_5openalex-snapshot
Predictive Preload at Fixed Preemption Points for Microcontrollers with Hard Real-Time Requirements
inferred← citeshttps://doi.org/10.1007/978-3-642-24349-3_7openalex-snapshot
Reconciling Compilation and Timing Analysis
inferred← citeshttps://doi.org/10.1007/978-3-658-37751-9_10openalex-snapshot
Echtzeitfähige Ethernet-Kommunikation in automobilen Multicore-Systemen mit hierarchischem Speicherlayout
inferred← citeshttps://doi.org/10.1007/s10617-005-1199-zopenalex-snapshot
Single Source Design Environment for Embedded Systems Based on SystemC
inferred← citeshttps://doi.org/10.1007/s11241-010-9101-xopenalex-snapshot
A compiler framework for the reduction of worst-case execution times
inferred← citeshttps://doi.org/10.1007/s11241-012-9159-8openalex-snapshot
Data cache organization for accurate timing analysis
inferred← citeshttps://doi.org/10.1007/s11265-015-1099-9openalex-snapshot
A Novel Design of Software System on Chip for Embedded System
inferred← citeshttps://doi.org/10.1016/j.sysarc.2013.09.009openalex-snapshot
A comparison of instruction memories from the WCET perspective
inferred← citeshttps://doi.org/10.1109/access.2022.3144044openalex-snapshot
iSotEE: A Hypervisor Middleware for IoT-Enabled Resource-Constrained Reliable Systems
inferred← citeshttps://doi.org/10.1109/clei.2015.7359462openalex-snapshot
Scratchpad memory management using data-prefetching
inferred← citeshttps://doi.org/10.1109/ecrts.2007.37openalex-snapshot
WCET-Directed Dynamic Scratchpad Memory Allocation of Data
inferred← citeshttps://doi.org/10.1109/hpcc.2012.211openalex-snapshot
Impact of Instruction Cache and Different Instruction Scratchpads on the WCET Estimate
inferred← citeshttps://doi.org/10.1109/hpec.2017.8091060openalex-snapshot
Leakage energy reduction for hard real-time caches
inferred← citeshttps://doi.org/10.1109/icie.2009.45openalex-snapshot
WCET-Guided Optimal Data Allocation to Scratchpad Memory
inferred← citeshttps://doi.org/10.1109/iecon.2011.6119761openalex-snapshot
Run-time scratch-pad memory management for embedded systems
inferred← citeshttps://doi.org/10.1109/isorc.2009.13openalex-snapshot
Thread-Local Scope Caching for Real-time Java
inferred← citeshttps://doi.org/10.1109/isorc.2014.48openalex-snapshot
WCET-Based Comparison of an Instruction Scratchpad and a Method Cache
inferred← citeshttps://doi.org/10.1109/isorc.2017.17openalex-snapshot
Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy
inferred← citeshttps://doi.org/10.1109/isorcw.2010.22openalex-snapshot
Towards a Time-Predictable Hierarchical Memory Architecture - Prefetching Options to be Explored
inferred← citeshttps://doi.org/10.1109/isorcw.2011.41openalex-snapshot
Using a Local Prefetch Strategy to Obtain Temporal Time Predictability
inferred← citeshttps://doi.org/10.1109/rtas.2008.11openalex-snapshot
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
inferred← citeshttps://doi.org/10.1109/rtss.2005.45openalex-snapshot
WCET Centric Data Allocation to Scratchpad Memory
inferred← citeshttps://doi.org/10.1109/rtss.2009.33openalex-snapshot
A Generic Framework for Soft Real-Time Program Executions on NAND Flash Memory in Multi-Tasking Embedded Systems
inferred← citeshttps://doi.org/10.1109/sbesc.2014.8openalex-snapshot
On the Influence of Shared Memory Contention in Real-Time Multicore Applications
inferred← citeshttps://doi.org/10.1109/stfssd.2009.10openalex-snapshot
Time-predictable Cache Organization
inferred← citeshttps://doi.org/10.1109/tc.2010.225openalex-snapshot
RT-PLRU: A New Paging Scheme for Real--Time Execution of Program Codes on NAND Flash Memory for Portable Media Players
inferred← citeshttps://doi.org/10.1109/tc.2013.70openalex-snapshot
HRT-PLRU: A New Paging Schemefor Executing Hard Real-Time Programson NAND Flash Memory
inferred← citeshttps://doi.org/10.1109/tvlsi.2006.878469openalex-snapshot
Overlay techniques for scratchpad memories in low power embedded processors
inferred← citeshttps://doi.org/10.1145/1289816.1289853openalex-snapshot
Compile-time decided instruction cache locking using worst-case execution paths
inferred← citeshttps://doi.org/10.1145/1289881.1289899openalex-snapshot
Scratch-pad memory allocation without compiler support for java applications
inferred← citeshttps://doi.org/10.1145/1622103.1622106openalex-snapshot
Acceleration of the L4/Fiasco microkernel using scratchpad memory
inferred← citeshttps://doi.org/10.1145/1629911.1630101openalex-snapshot
Optimal static WCET-aware scratchpad allocation of program code
inferred← citeshttps://doi.org/10.1145/1879021.1879043openalex-snapshot
Using NAND flash memory for executing large volume real-time programs in automotive embedded systems
inferred← citeshttps://doi.org/10.1145/2560033openalex-snapshot
Building timing predictable embedded systems
inferred← citeshttps://doi.org/10.1145/2744769.2744855openalex-snapshot
Improving worst-case cache performance through selective bypassing and register-indexed cache
inferred← citeshttps://doi.org/10.1145/2752801.2752803openalex-snapshot
Aligning single path loops to reduce the number of capacity cache misses
inferred← citeshttps://doi.org/10.1145/2997465.2997488openalex-snapshot
A Software Managed Stack Cache for Real-Time Systems
inferred← citeshttps://doi.org/10.1155/2009/758480openalex-snapshot
Time-Predictable Computer Architecture
inferred← citeshttps://doi.org/10.1201/9781420043839.ch1openalex-snapshot
Worst-Case Execution Time and Energy Analysis
inferred← citeshttps://doi.org/10.23919/date.2019.8714926openalex-snapshot
Scratchpad Memories with Ownership
inferred← citeshttps://doi.org/10.3929/ethz-a-005203573openalex-snapshot
On instruction-set generation for specialized processors
inferred← citeshttps://doi.org/10.4304/jsw.4.10.1053-1060openalex-snapshot
A Novel Operating System on Chip with Information Security Support for Embedded System
inferred← citeshttps://doi.org/10.5626/jcse.2019.13.2.39openalex-snapshot
Analysis of the Factors Influencing Architectural Time-Predictability of Superscalar Processors
inferred← citeshttps://doi.org/10.6100/ir630369openalex-snapshot
Dealing with dynamism in embedded system design:application scenarios
inferred← citeshttps://doi.org/10.6100/ir642808openalex-snapshot
Predictable embedded multiprocessor architecture for streaming applications
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.