On the public citation graph

Scratchpad memory: a design alternative for cache on-chip memory in embedded systems

0 signed · 152 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-5107-2openalex-snapshot
Memory Issues in Embedded Systems-on-Chip
inferredcites →https://doi.org/10.1109/4.509850openalex-snapshot
CACTI: an enhanced cache access and cycle time model
inferredcites →https://doi.org/10.1109/54.922799openalex-snapshot
Embedded DRAM development: Technology, physical design, and application issues
inferredcites →https://doi.org/10.1109/micro.1997.645809openalex-snapshot
The filter cache: an energy efficient memory structure

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/9781118577585.biblioopenalex-snapshot
Bibliography
inferred← citeshttps://doi.org/10.1007/978-1-4614-4992-8_2openalex-snapshot
Background and Related Work
inferred← citeshttps://doi.org/10.1007/978-90-481-9528-2_4openalex-snapshot
Overall Framework for Exploration
inferred← citeshttps://doi.org/10.1007/978-90-481-9528-2_6openalex-snapshot
Multi-threading in Uni-threaded Processor
inferred← citeshttps://doi.org/10.1007/978-90-481-9528-2_7openalex-snapshot
Handling Irregular Indexed Arrays and Dynamically Accessed Data on Scratchpad Memory Organisations
inferred← citeshttps://doi.org/10.1007/978-94-017-7267-9_41openalex-snapshot
Introduction to Hardware/Software Codesign
inferred← citeshttps://doi.org/10.1007/s11265-009-0362-3openalex-snapshot
Variable Partitioning and Scheduling for MPSoC with Virtually Shared Scratch Pad Memory
inferred← citeshttps://doi.org/10.1016/b978-0-12-801379-3.00007-3openalex-snapshot
Sustainable Software Design
inferred← citeshttps://doi.org/10.1016/b978-012379751-3.50034-5openalex-snapshot
References
inferred← citeshttps://doi.org/10.1109/acssc.2010.5757922openalex-snapshot
A PRET architecture supporting concurrent programs with composable timing properties
inferred← citeshttps://doi.org/10.1109/asap.2008.4580191openalex-snapshot
Lightweight DMA management mechanisms for multiprocessors on FPGA
inferred← citeshttps://doi.org/10.1109/asap.2008.4580192openalex-snapshot
Memory copies in multi-level memory systems
inferred← citeshttps://doi.org/10.1109/asap.2013.6567591openalex-snapshot
A highly efficient, thread-safe software cache implementation for tightly-coupled multicore clusters
inferred← citeshttps://doi.org/10.1109/asap.2013.6567593openalex-snapshot
Hybrid SPM-cache architectures to achieve high time predictability and performance
inferred← citeshttps://doi.org/10.1109/asap.2014.6868666openalex-snapshot
Exploring DMA-assisted prefetching strategies for software caches on multicore clusters
inferred← citeshttps://doi.org/10.1109/asap.2016.7760774openalex-snapshot
Efficient pointer management of stack data for software managed multicores
inferred← citeshttps://doi.org/10.1109/aspdac.2006.1594753openalex-snapshot
A novel instruction scratchpad memory optimization method based on concomitance metric
inferred← citeshttps://doi.org/10.1109/aspdac.2006.1594787openalex-snapshot
Analysis of scratch-pad and data-cache performance using statistical methods
inferred← citeshttps://doi.org/10.1109/aspdac.2009.4796503openalex-snapshot
HitME: Low power Hit MEmory buffer for embedded systems
inferred← citeshttps://doi.org/10.1109/aspdac.2009.4796548openalex-snapshot
A software solution for dynamic stack management on scratch pad memory
inferred← citeshttps://doi.org/10.1109/aspdac.2012.6164955openalex-snapshot
An integrated and automated memory optimization flow for FPGA behavioral synthesis
inferred← citeshttps://doi.org/10.1109/aspdac.2012.6164965openalex-snapshot
When to forget: A system-level perspective on STT-RAMs
inferred← citeshttps://doi.org/10.1109/asqed.2013.6643570openalex-snapshot
High-quality data assignment to hierarchical memory organizations for multidimensional signal processing
inferred← citeshttps://doi.org/10.1109/candar.2013.60openalex-snapshot
An XOR-Based Approach to Merging Entries for Instruction Register Files
inferred← citeshttps://doi.org/10.1109/cases.2013.6662527openalex-snapshot
SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems
inferred← citeshttps://doi.org/10.1109/cgo.2005.13openalex-snapshot
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
inferred← citeshttps://doi.org/10.1109/cgo.2013.6495003openalex-snapshot
Improving data access efficiency by using a tagless access buffer (TAB)
inferred← citeshttps://doi.org/10.1109/cicn.2013.95openalex-snapshot
A New Efficient Replacement Policy for Scratch Pad Memory
inferred← citeshttps://doi.org/10.1109/cit.2010.389openalex-snapshot
A Virtual Timing Device for Program Performance Analysis
inferred← citeshttps://doi.org/10.1109/csae.2012.6272840openalex-snapshot
New algorithms to improve code overlay performance
inferred← citeshttps://doi.org/10.1109/cse.2009.350openalex-snapshot
A Region-Based Allocation Approach for Page-Based Scratch-Pad Memory in Embedded Systems
inferred← citeshttps://doi.org/10.1109/cse.2013.114openalex-snapshot
Local-Memory-Based Integrity Checking for Embedded Systems
inferred← citeshttps://doi.org/10.1109/date.2004.1269069openalex-snapshot
Cache-aware scratchpad allocation algorithm
inferred← citeshttps://doi.org/10.1109/date.2005.183openalex-snapshot
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software
inferred← citeshttps://doi.org/10.1109/date.2006.243733openalex-snapshot
Distributed Loop Controller Architecture for Multi-threading in Uni-threaded VLIW Processors
inferred← citeshttps://doi.org/10.1109/date.2006.244091openalex-snapshot
Integrated Data Relocation and Bus Reconfiguration for Adaptive System-on-Chip Platforms
inferred← citeshttps://doi.org/10.1109/date.2007.364484openalex-snapshot
DRIM : A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for Embedded Systems
inferred← citeshttps://doi.org/10.1109/date.2009.5090797openalex-snapshot
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications
inferred← citeshttps://doi.org/10.1109/date.2011.5763127openalex-snapshot
Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory
inferred← citeshttps://doi.org/10.1109/dsd.2011.80openalex-snapshot
Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling
inferred← citeshttps://doi.org/10.1109/dsd.2015.77openalex-snapshot
Dynamic Detection and Mitigation of DMA Races in MPSoCs
inferred← citeshttps://doi.org/10.1109/ecrts.2005.34openalex-snapshot
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
inferred← citeshttps://doi.org/10.1109/ecrts.2006.32openalex-snapshot
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
inferred← citeshttps://doi.org/10.1109/ecrts.2013.28openalex-snapshot
A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems
inferred← citeshttps://doi.org/10.1109/estmed.2005.1518087openalex-snapshot
Scratchpad sharing strategies for multiprocess embedded systems: a first approach
inferred← citeshttps://doi.org/10.1109/estmed.2007.4375794openalex-snapshot
Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories
inferred← citeshttps://doi.org/10.1109/estmed.2008.4697003openalex-snapshot
A framework for memory-aware multimedia application mapping on chip-multiprocessors
inferred← citeshttps://doi.org/10.1109/estmed.2009.5336815openalex-snapshot
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications
inferred← citeshttps://doi.org/10.1109/estmed.2009.5336819openalex-snapshot
Optimal stack frame placement and transfer for energy reduction targeting embedded processors with scratch-pad memories
inferred← citeshttps://doi.org/10.1109/hpcc.2012.14openalex-snapshot
Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression
inferred← citeshttps://doi.org/10.1109/hpcc.2012.221openalex-snapshot
Address-Locking Cache: A Flexible on Chip Memory Implementation for Embedded System
inferred← citeshttps://doi.org/10.1109/icassp.2009.4959662openalex-snapshot
Automatic generation of maps of memory accesses for energy-aware memory management
inferred← citeshttps://doi.org/10.1109/icassp.2014.6854559openalex-snapshot
Leakage-aware scratch-pad memory banking for embedded multidimensional signal processing
inferred← citeshttps://doi.org/10.1109/iccad.2003.159748openalex-snapshot
Dynamic platform management for configurable platform-based System-on-Chips
inferred← citeshttps://doi.org/10.1109/iccad.2004.1382603openalex-snapshot
Hardware/software managed scratchpad memory for embedded system
inferred← citeshttps://doi.org/10.1109/iccad.2008.4681632openalex-snapshot
SPM management using Markov chain based data access prediction
inferred← citeshttps://doi.org/10.1109/icccnt.2012.6396100openalex-snapshot
Usage of scratchpad memory in embedded systems — State of art
inferred← citeshttps://doi.org/10.1109/iccd.2005.111openalex-snapshot
Using scratchpad to exploit object locality in Java
inferred← citeshttps://doi.org/10.1109/iccd.2010.5647616openalex-snapshot
Thermal-aware scratchpad memory design and allocation
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378622openalex-snapshot
A PRET microarchitecture implementation with repeatable timing and competitive performance
inferred← citeshttps://doi.org/10.1109/iccet.2009.50openalex-snapshot
Data Allocation for SPM Based on Knapsack Problem
inferred← citeshttps://doi.org/10.1109/iccse.2012.64openalex-snapshot
ILP-based Memory-Aware Mapping Optimization for MPSoCs
inferred← citeshttps://doi.org/10.1109/icecs.2015.7440311openalex-snapshot
Differentiation of MPSoCs message classes using multiple NoCs
inferred← citeshttps://doi.org/10.1109/icess.2008.93openalex-snapshot
A Virus Detection Framework based on SPMOS
inferred← citeshttps://doi.org/10.1109/icmel.2006.1650978openalex-snapshot
System-on-Chip Design: Engineering or Art
inferred← citeshttps://doi.org/10.1109/icnsc.2008.4525484openalex-snapshot
An Alternative Choice of Scratch-Pad Memory for Energy Optimization in Embedded System
inferred← citeshttps://doi.org/10.1109/icpp.2011.79openalex-snapshot
Optimal Data Allocation for Scratch-Pad Memory on Embedded Multi-core Systems
inferred← citeshttps://doi.org/10.1109/icprime.2012.6208343openalex-snapshot
Scratchpad memory-global power optimization
inferred← citeshttps://doi.org/10.1109/icsamos.2009.5289226openalex-snapshot
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability
inferred← citeshttps://doi.org/10.1109/icycs.2008.272openalex-snapshot
The P2P Communication Model for a Local Memory based Multi-core Processor
inferred← citeshttps://doi.org/10.1109/idt.2013.6727141openalex-snapshot
Memristor for energy efficient wireless sensor node
inferred← citeshttps://doi.org/10.1109/interact.2012.6339622openalex-snapshot
MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536314openalex-snapshot
Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations
inferred← citeshttps://doi.org/10.1109/iscas.2013.6572078openalex-snapshot
Designing scratchpad memory architecture with emerging STT-RAM memory technologies
inferred← citeshttps://doi.org/10.1109/islped.2011.5993648openalex-snapshot
An integrated optimization framework for reducing the energy consumption of embedded real-time applications
inferred← citeshttps://doi.org/10.1109/isqed.2006.115openalex-snapshot
Shared Scratch-Pad Memory Space Management
inferred← citeshttps://doi.org/10.1109/isqed.2008.4479830openalex-snapshot
A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm
inferred← citeshttps://doi.org/10.1109/isqed.2014.6783389openalex-snapshot
Energy-aware scratch-pad memory partitioning for embedded systems
inferred← citeshttps://doi.org/10.1109/issoc.2010.5625536openalex-snapshot
Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis
inferred← citeshttps://doi.org/10.1109/isvlsi.2010.66openalex-snapshot
A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency
inferred← citeshttps://doi.org/10.1109/itng.2008.226openalex-snapshot
Performance Analysis of Cache and Scratchpad Memory in an Embedded High Performance Processor
inferred← citeshttps://doi.org/10.1109/iwnas.2006.17openalex-snapshot
Assigning Program To Cache-Aware Scratchpad Concerning The Influence Of The Whole Embedded System
inferred← citeshttps://doi.org/10.1109/les.2013.2296779openalex-snapshot
PEG-C: Performance Enhancement Guaranteed Cache for Hard Real-Time Systems
inferred← citeshttps://doi.org/10.1109/mobhoc.2009.5336913openalex-snapshot
Improving the reliability of embedded systems with cache and SPM
inferred← citeshttps://doi.org/10.1109/mwscas.2013.6674781openalex-snapshot
Scratch-pad memory banking for energy reduction in embedded signal processing systems
inferred← citeshttps://doi.org/10.1109/nas.2010.14openalex-snapshot
Design Space Exploration for Memory Subsystems of VLIW Architectures
inferred← citeshttps://doi.org/10.1109/newcas.2005.1496685openalex-snapshot
Balancing Scratchpad and Cache in Embedded-Systems for Power and Speed Performance
inferred← citeshttps://doi.org/10.1109/niss.2009.265openalex-snapshot
Pattern Description for the Energy-Efficient Code Generation
inferred← citeshttps://doi.org/10.1109/pdcat.2011.61openalex-snapshot
Optimizing Web Browser on Many-Core Architectures
inferred← citeshttps://doi.org/10.1109/pdp.2007.67openalex-snapshot
Pretenuring in Java by Object Lifetime and Reference Density Using Scratch-Pad Memory
inferred← citeshttps://doi.org/10.1109/percom.2009.4912829openalex-snapshot
Efficient utilization of scratch-pad memory for embedded systems
inferred← citeshttps://doi.org/10.1109/reconfig.2012.6416747openalex-snapshot
Exploring hardware work queue support for lightweight threads in MPSoCs
inferred← citeshttps://doi.org/10.1109/rsp.2012.6380699openalex-snapshot
Challenges in software development for multicore System-on-Chip development
inferred← citeshttps://doi.org/10.1109/rtas.2012.22openalex-snapshot
Leveraging both Data Cache and Scratchpad Memory through Synergetic Data Allocation
inferred← citeshttps://doi.org/10.1109/rtas.2012.23openalex-snapshot
Developing Predictable Real-Time Embedded Systems Using AnvilJ
inferred← citeshttps://doi.org/10.1109/rtcsa.2009.51openalex-snapshot
ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems
inferred← citeshttps://doi.org/10.1109/rtcsa.2012.20openalex-snapshot
Optimizing Data Allocation for Loops on Embedded Systems with Scratch-Pad Memory
inferred← citeshttps://doi.org/10.1109/rtcsa.2013.6732207openalex-snapshot
Design space exploration for low-power memory systems in embedded signal processing applications
inferred← citeshttps://doi.org/10.1109/rtss.2005.45openalex-snapshot
WCET Centric Data Allocation to Scratchpad Memory
inferred← citeshttps://doi.org/10.1109/rtss.2008.9openalex-snapshot
Predictable Out-of-Order Execution Using Virtual Traces
inferred← citeshttps://doi.org/10.1109/samos.2012.6404195openalex-snapshot
Efficient computing in cyber-physical systems
inferred← citeshttps://doi.org/10.1109/sc.2012.61openalex-snapshot
Hardware-software coherence protocol for the coexistence of caches and local memories
inferred← citeshttps://doi.org/10.1109/sc.companion.2012.111openalex-snapshot
Efficient HPC Data Motion via Scratchpad Memory
inferred← citeshttps://doi.org/10.1109/socc.2009.5335657openalex-snapshot
An efficient software cache for H.264 motion compensation
inferred← citeshttps://doi.org/10.1109/soli.2009.5203929openalex-snapshot
Alternative choice for energy optimization in embedded system
inferred← citeshttps://doi.org/10.1109/tc.2008.168openalex-snapshot
Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures
inferred← citeshttps://doi.org/10.1109/tc.2009.188openalex-snapshot
Scratchpad Memory Management Techniques for Code in Embedded Systems without an MMU
inferred← citeshttps://doi.org/10.1109/tc.2010.199openalex-snapshot
An OpenMP Compiler for Efficient Use of Distributed Scratchpad Memory in MPSoCs
inferred← citeshttps://doi.org/10.1109/tcad.2005.852299openalex-snapshot
An efficient profile-based algorithm for scratchpad memory partitioning
inferred← citeshttps://doi.org/10.1109/tcad.2005.859523openalex-snapshot
Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems
inferred← citeshttps://doi.org/10.1109/tcad.2009.2014002openalex-snapshot
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications
inferred← citeshttps://doi.org/10.1109/tcad.2009.2030592openalex-snapshot
A Software-Only Solution to Use Scratch Pads for Stack Data
inferred← citeshttps://doi.org/10.1109/tcad.2013.2238990openalex-snapshot
Data Placement and Duplication for Embedded Multicore Systems With Scratch Pad Memory
inferred← citeshttps://doi.org/10.1109/tencon.2011.6129083openalex-snapshot
Replacement policies for scratch pad memory in embedded systems
inferred← citeshttps://doi.org/10.1109/tifs.2013.2266095openalex-snapshot
Monitoring Integrity Using Limited Local Memory
inferred← citeshttps://doi.org/10.1109/trustcom.2011.143openalex-snapshot
Optimal Data Placement for Memory Architectures with Scratch-Pad Memories
inferred← citeshttps://doi.org/10.1109/trustcom.2013.167openalex-snapshot
Thermal-Aware On-Chip Memory Architecture Exploration
inferred← citeshttps://doi.org/10.1109/tsp.2012.2189768openalex-snapshot
Minimizing Access Cost for Multiple Types of Memory Units in Embedded Systems Through Data Allocation and Scheduling
inferred← citeshttps://doi.org/10.1109/tvlsi.2006.878469openalex-snapshot
Overlay techniques for scratchpad memories in low power embedded processors
inferred← citeshttps://doi.org/10.1109/tvlsi.2006.878470openalex-snapshot
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2001940openalex-snapshot
Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips
inferred← citeshttps://doi.org/10.1109/tvlsi.2011.2163534openalex-snapshot
Run-Time Reconfiguration of Expandable Cache for Embedded Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2012.2202700openalex-snapshot
Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory
inferred← citeshttps://doi.org/10.1109/vdat.2009.5158097openalex-snapshot
Allocation of scratch-pad memory in priority-based multi-task systems
inferred← citeshttps://doi.org/10.1109/vdat.2010.5496725openalex-snapshot
Inter and intra kernel reuse analysis driven pipelining on Chip-Multiprocessors
inferred← citeshttps://doi.org/10.1109/vlsisoc.2010.5642695openalex-snapshot
A novel reconfigurable scratchpad memory for audio applications on cost-effective SoC
inferred← citeshttps://doi.org/10.1109/wsc.2005.1574300openalex-snapshot
Performance Analysis of Binary Code Protection
inferred← citeshttps://doi.org/10.11591/ijres.v6.i2.pp69-81openalex-snapshot
Software and Hardware for managing Scratch Pad Memory
inferred← citeshttps://doi.org/10.11591/ijres.v7.i1.pp21-33openalex-snapshot
Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator
inferred← citeshttps://doi.org/10.1201/9781439807637.ch11openalex-snapshot
Power-Aware Embedded Computing
inferred← citeshttps://doi.org/10.12681/eadd/17713openalex-snapshot
Ανάπτυξη αρχιτεκτονικών και τεχνικών μεταφραστών για διαχείριση μνήμης σε ενσωματωμένα συστήματα
inferred← citeshttps://doi.org/10.12794/metadc500021openalex-snapshot
Low Leakage Asymmetric Stacked Sram Cell
inferred← citeshttps://doi.org/10.1360/zf2013-43-7-932openalex-snapshot
基于置换图的便笺存储器分配
inferred← citeshttps://doi.org/10.18130/v3479copenalex-snapshot
Trace-Based Dynamic Binary Parallelization
inferred← citeshttps://doi.org/10.18178/wcse.2020.06.043openalex-snapshot
Real-time Task Allocation Based on Variable Scratchpad Memory
inferred← citeshttps://doi.org/10.31390/gradschool_dissertations.716openalex-snapshot
Compilation and Scheduling Techniques for Embedded Systems
inferred← citeshttps://doi.org/10.32657/10356/19286openalex-snapshot
Profile driven schemes for energy-sensitive cache hierarchy
inferred← citeshttps://doi.org/10.32657/10356/47483openalex-snapshot
Customizable instruction cache hierarchy for embedded systems
inferred← citeshttps://doi.org/10.3384/diss.diva-130723openalex-snapshot
Design of Energy-Efficient High-Performance ASIP-DSP Platforms
inferred← citeshttps://doi.org/10.47749/t/unicamp.2010.770809openalex-snapshot
Projeto de caches de matrizes particionados baseados em rastros de acesso à memória para sistemas embarcados
inferred← citeshttps://doi.org/10.5120/17040-7350openalex-snapshot
An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC
inferred← citeshttps://doi.org/10.5772/8876openalex-snapshot
Power-Aware Memory Allocation for Embedded Data-Intensive Signal Processing Applications
inferred← citeshttps://doi.org/10.5821/dissertation-2117-113291openalex-snapshot
Enabling caches in probabilistic timing analysis
inferred← citeshttps://doi.org/10.5821/dissertation-2117-114436openalex-snapshot
Probabilistically time-analyzable complex processor designs
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94621openalex-snapshot
Software caching techniques and hardware optimizations for on-chip local memories
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95566openalex-snapshot
A novel access pattern-based multi-core memory architecture
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96004openalex-snapshot
Transparent management of scratchpad memories in shared memory programming models
inferred← citeshttps://doi.org/10.6028/nist.tn.1867openalex-snapshot
Time-Aware Applications, Computers, and Communication Systems (TAACCS)
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.