On the public citation graph
Distributed Loop Controller Architecture for Multi-threading in Uni-threaded VLIW Processors
0 signed · 35 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11532378_4openalex-snapshot
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism
inferredcites →https://doi.org/10.1007/3-540-44687-7_31openalex-snapshot
CRISP: A Template for Reconfigurable Instruction Set Processors
inferredcites →https://doi.org/10.1007/3-540-45307-5_17openalex-snapshot
Weld: A Multithreading Technique Towards Latency-tolerant VLIW Processors
inferredcites →https://doi.org/10.1023/a:1007554627716openalex-snapshot
Generation of Efficient Nested Loops from Polyhedra
inferredcites →https://doi.org/10.1109/asap.2004.1342472openalex-snapshot
Optimizing the memory bandwidth with loop morphing
inferredcites →https://doi.org/10.1109/asap.2005.52openalex-snapshot
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application
inferredcites →https://doi.org/10.1109/codes.2002.1003604openalex-snapshot
Scratchpad memory: a design alternative for cache on-chip memory in embedded systems
inferredcites →https://doi.org/10.1109/date.2002.998305openalex-snapshot
An efficient compiler technique for code size reduction using reduced bit-width ISAs
inferredcites →https://doi.org/10.1109/date.2002.998306openalex-snapshot
Assigning program and data objects to scratchpad for energy reduction
inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot
Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1109/ispass.2005.1430566openalex-snapshot
Partitioning Multi-Threaded Processors with a Large Number of Threads
inferredcites →https://doi.org/10.1109/isscc.2005.1493857openalex-snapshot
Ambient intelligence: gigascale dreams and nanoscale realities
inferredcites →https://doi.org/10.1109/micro.1996.566462openalex-snapshot
Instruction fetch mechanisms for VLIW architectures with compressed encodings
inferredcites →https://doi.org/10.1109/micro.2001.991124openalex-snapshot
Enhancing loop buffering of media and telecommunications applications using low-overhead predication
inferredcites →https://doi.org/10.1109/real.2004.18openalex-snapshot
Design Style Case Study for Embedded Multi Media Compute Nodes
inferredcites →https://doi.org/10.1109/tc.2005.92openalex-snapshot
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors
inferredcites →https://doi.org/10.1109/tvlsi.2004.824299openalex-snapshot
Compiler-directed scratch pad memory optimization for embedded multiprocessors
inferredcites →https://doi.org/10.1145/502217.502254openalex-snapshot
Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads
inferredcites →https://doi.org/10.1145/774572.774669openalex-snapshot
Synthesis of customized loop caches for core-based embedded systems
inferredcites →https://doi.org/10.5555/1015090.1015311openalex-snapshot
Instruction buffering exploration for low energy VLIWs with instruction clusters
inferredcites →https://doi.org/10.5555/243846.243886openalex-snapshot
Instruction fetch mechanisms for VLIW architectures with compressed encodings
inferredcites →https://doi.org/10.5555/882452.874375openalex-snapshot
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs
inferredcites →https://doi.org/10.5555/882452.874376openalex-snapshot
Assigning Program and Data Objects to Scratchpad for Energy Reduction
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-540-77560-7_14openalex-snapshot
Coffee: COmpiler Framework for Energy-Aware Exploration
inferred← citeshttps://doi.org/10.1007/s11265-012-0694-2openalex-snapshot
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems
inferred← citeshttps://doi.org/10.1007/s11265-013-0749-zopenalex-snapshot
Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems
inferred← citeshttps://doi.org/10.1109/icecs.2012.6463518openalex-snapshot
IMOSIM: Exploration tool for Instruction Memory Organisations based on accurate cycle-level energy modelling
inferred← citeshttps://doi.org/10.1109/isvlsi.2011.62openalex-snapshot
AIFSP: An Adaptive Instruction Flow Stream Processor
inferred← citeshttps://doi.org/10.1109/iwia.2010.10openalex-snapshot
[2010] Energy Efficiency Using Loop Buffer based Instruction Memory Organizations
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2013.6673278openalex-snapshot
Energy impact in the design space exploration of loop buffer schemes in embedded systems
inferred← citeshttps://doi.org/10.1145/1269843.1269851openalex-snapshot
Systematic intermediate sequence removal for reduced memory accesses
inferred← citeshttps://doi.org/10.1145/1400112.1400116openalex-snapshot
Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.