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VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0022-0000(86)90028-0openalex-snapshot
On the possibility and impossibility of achieving clock synchronization
inferredcites →https://doi.org/10.1109/12.8720openalex-snapshot
Transmission delays in hardware clock synchronization
inferredcites →https://doi.org/10.1109/5.362752openalex-snapshot
Asynchronous design methodologies: an overview
inferredcites →https://doi.org/10.1109/5.929649openalex-snapshot
Clock distribution networks in synchronous digital integrated circuits
inferredcites →https://doi.org/10.1109/dasc.1997.635030openalex-snapshot
Single chip fault tolerant clock for integrated modular avionics
inferredcites →https://doi.org/10.1109/dsn.2002.1028901openalex-snapshot
Impact of deep submicron technology on dependability of VLSI circuits
inferredcites →https://doi.org/10.1109/edcc.2006.11openalex-snapshot
Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip
inferredcites →https://doi.org/10.1109/iscas.1991.176225openalex-snapshot
An all digital phase locked loop fault tolerant clock
inferredcites →https://doi.org/10.1109/jssc.2002.803943openalex-snapshot
The implementation of the Itanium 2 microprocessor
inferredcites →https://doi.org/10.1109/vts.2005.52openalex-snapshot
Low cost scheme for on-line clock skew compensation
inferredcites →https://doi.org/10.1145/764808.764819openalex-snapshot
Interconnected rings and oscillators as gigahertz clock distribution nets
inferredcites →https://doi.org/10.13140/rg.2.1.4128.7843openalex-snapshot
Globally-Asynchronous Locally-Synchronous Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-642-05118-0_40openalex-snapshot
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
inferred← citeshttps://doi.org/10.1007/s00446-009-0080-xopenalex-snapshot
The Theta-Model: achieving synchrony without clocks
inferred← citeshttps://doi.org/10.1007/s00446-011-0151-7openalex-snapshot
Reconciling fault-tolerant distributed computing and systems-on-chip
inferred← citeshttps://doi.org/10.1007/s00502-006-0409-0openalex-snapshot
FIT-IT-Projekt DARTS: dezentrale fehlertolerante Taktgenerierung
inferred← citeshttps://doi.org/10.1016/j.jcss.2014.01.001openalex-snapshot
Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip
inferred← citeshttps://doi.org/10.1016/j.tcs.2010.08.001openalex-snapshot
The Asynchronous Bounded-Cycle model
inferred← citeshttps://doi.org/10.1080/00207721.2013.822607openalex-snapshot
Energy-aware feedback control for a H.264 video decoder
inferred← citeshttps://doi.org/10.1109/async.2009.15openalex-snapshot
On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme
inferred← citeshttps://doi.org/10.1109/austrochip62761.2024.10716225openalex-snapshot
Synchronizing Independent Ring Oscillators on an FPGA
inferred← citeshttps://doi.org/10.1109/dsd.2008.65openalex-snapshot
Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip
inferred← citeshttps://doi.org/10.1109/dsnw.2010.5542607openalex-snapshot
Towards self-timed logic in the Time-Triggered Protocol
inferred← citeshttps://doi.org/10.1109/edcc.2010.35openalex-snapshot
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining
inferred← citeshttps://doi.org/10.1109/idt.2007.4437442openalex-snapshot
Adopting the Scan Approach for a Fault Tolerant Asynchronous Clock Generation Circuit
inferred← citeshttps://doi.org/10.1109/isvlsi.2016.88openalex-snapshot
Fault-Tolerant Clock Synchronization with High Precision
inferred← citeshttps://doi.org/10.1145/1400751.1400815openalex-snapshot
The asynchronous bounded-cycle model
inferred← citeshttps://doi.org/10.1145/2560561openalex-snapshot
Fault-tolerant algorithms for tick-generation in asynchronous logic
inferred← citeshttps://doi.org/10.1155/2011/936712openalex-snapshot
VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation
inferred← citeshttps://doi.org/10.1155/2011/972375openalex-snapshot
On Self-Timed Circuits in Real-Time Systems
inferred← citeshttps://doi.org/10.32657/10356/14572openalex-snapshot
Adaptive computing for In Silico recognition of hormone response elements
inferred← citeshttps://doi.org/10.4230/dagsemproc.08371.4openalex-snapshot
Implications of VLSI Fault Models and Distributed Systems Failure Models – A hardware designer's view
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