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Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/bf01660033openalex-snapshot
On the existence of delay-insensitive fair arbiters: Trace theory and its limitations
inferredcites →https://doi.org/10.1007/bf01660034openalex-snapshot
Compiling communicating processes into delay-insensitive VLSI circuits
inferredcites →https://doi.org/10.1007/bf01798957openalex-snapshot
Consensus algorithms with one-bit messages
inferredcites →https://doi.org/10.1016/0022-0000(86)90028-0openalex-snapshot
On the possibility and impossibility of achieving clock synchronization
inferredcites →https://doi.org/10.1023/a:1008150426963openalex-snapshot
A Network Time Interface M-Module for Distributing GPS-Time over LANs
inferredcites →https://doi.org/10.1109/12.2183openalex-snapshot
The MAFT architecture for distributed fault tolerance
inferredcites →https://doi.org/10.1109/2.248873openalex-snapshot
TTP-a protocol for fault-tolerant real-time systems
inferredcites →https://doi.org/10.1109/5.362752openalex-snapshot
Asynchronous design methodologies: an overview
inferredcites →https://doi.org/10.1109/5.929649openalex-snapshot
Clock distribution networks in synchronous digital integrated circuits
inferredcites →https://doi.org/10.1109/async.2005.29openalex-snapshot
Self-Timed Circuitry for Global Clocking
inferredcites →https://doi.org/10.1109/dftvs.2004.1347838openalex-snapshot
Modeling and analysis of crosstalk coupling effect on the victim interconnect using the ABCD network model
inferredcites →https://doi.org/10.1109/dftvs.2004.1347862openalex-snapshot
Accurate estimation of soft error rate (SER) in VLSI circuits
inferredcites →https://doi.org/10.1109/dsn.2001.941391openalex-snapshot
How to model link failures: a perception-based fault model
inferredcites →https://doi.org/10.1109/dsn.2002.1028901openalex-snapshot
Impact of deep submicron technology on dependability of VLSI circuits
inferredcites →https://doi.org/10.1109/edcc.2006.11openalex-snapshot
Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip
inferredcites →https://doi.org/10.1109/icecs.2001.957589openalex-snapshot
Analysis of clock distribution networks in the presence of crosstalk and groundbounce
inferredcites →https://doi.org/10.1109/mc.2005.70openalex-snapshot
Robust system design with built-in soft-error resilience
inferredcites →https://doi.org/10.1145/359545.359563openalex-snapshot
Time, clocks, and the ordering of events in a distributed system
inferredcites →https://doi.org/10.1145/764808.764819openalex-snapshot
Interconnected rings and oscillators as gigahertz clock distribution nets
inferredcites →https://doi.org/10.13140/rg.2.1.4128.7843openalex-snapshot
Globally-Asynchronous Locally-Synchronous Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Tutorial on Parameterized Model Checking of Fault-Tolerant Distributed Algorithms
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Optimal Message-Driven Implementation of Omega with Mute Processes
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A Metastability-Free Multi-synchronous Communication Scheme for SoCs
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Weak Synchrony Models and Failure Detectors for Message Passing (k-)Set Agreement
inferred← citeshttps://doi.org/10.1007/978-3-642-11266-9_5openalex-snapshot
Clock Synchronization: Open Problems in Theory and Practice
inferred← citeshttps://doi.org/10.1007/978-3-642-15297-9_5openalex-snapshot
Synchrony and Time in Fault-Tolerant Distributed Algorithms
inferred← citeshttps://doi.org/10.1007/978-3-642-24550-3_14openalex-snapshot
Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation
inferred← citeshttps://doi.org/10.1007/s00446-007-0026-0openalex-snapshot
Booting clock synchronization in partially synchronous systems with hybrid process and link failures
inferred← citeshttps://doi.org/10.1007/s00446-009-0080-xopenalex-snapshot
The Theta-Model: achieving synchrony without clocks
inferred← citeshttps://doi.org/10.1007/s00446-011-0151-7openalex-snapshot
Reconciling fault-tolerant distributed computing and systems-on-chip
inferred← citeshttps://doi.org/10.1007/s00502-006-0409-0openalex-snapshot
FIT-IT-Projekt DARTS: dezentrale fehlertolerante Taktgenerierung
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Generation of a fault-tolerant clock through redundant crystal oscillators
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The Asynchronous Bounded-Cycle model
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On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme
inferred← citeshttps://doi.org/10.1109/dft.2006.67openalex-snapshot
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
inferred← citeshttps://doi.org/10.1109/dsd.2008.65openalex-snapshot
Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip
inferred← citeshttps://doi.org/10.1109/dsd.2009.223openalex-snapshot
ARROW - A Generic Hardware Fault Injection Tool for NoCs
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Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip
inferred← citeshttps://doi.org/10.1109/edcc.2010.35openalex-snapshot
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining
inferred← citeshttps://doi.org/10.1145/1400751.1400815openalex-snapshot
The asynchronous bounded-cycle model
inferred← citeshttps://doi.org/10.1145/1462187.1462191openalex-snapshot
Optimal message-driven implementations of omega with mute processes
inferred← citeshttps://doi.org/10.1145/1582716.1582730openalex-snapshot
Tight bounds for clock synchronization
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Tight bounds for clock synchronization
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Fault-tolerant algorithms for tick-generation in asynchronous logic
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VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation
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Synchronization and symmetry breaking in distributed systems
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Implications of VLSI Fault Models and Distributed Systems Failure Models – A hardware designer's view
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Fault-tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation
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Counter Attack on Byzantine Generals: Parameterized Model Checking of Fault-tolerant Distributed Algorithms
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