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Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard

https://doi.org/10.1109/dftvs.2005.41

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-45126-6_12openalex-snapshot

Fault Based Cryptanalysis of the Advanced Encryption Standard (AES)

inferredcites →https://doi.org/10.1007/978-3-540-45238-6_10openalex-snapshot

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers

inferredcites →https://doi.org/10.1007/978-3-540-45238-6_27openalex-snapshot

Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs

inferredcites →https://doi.org/10.1007/978-3-540-45238-6_7openalex-snapshot

A Differential Fault Attack Technique against SPN Structures, with Application to the AES and Khazad

inferredcites →https://doi.org/10.1007/bfb0052259openalex-snapshot

Differential fault analysis of secret key cryptosystems

inferredcites →https://doi.org/10.1007/s001450010016openalex-snapshot

On the Importance of Eliminating Errors in Cryptographic Computations

inferredcites →https://doi.org/10.1080/0161-110291890876openalex-snapshot

THE ADVANCED ENCRYPTION STANDARD

inferredcites →https://doi.org/10.1109/dftvs.2001.966796openalex-snapshot

Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture

inferredcites →https://doi.org/10.1109/dftvs.2003.1250101openalex-snapshot

Detecting and locating faults in VLSI implementations of the Advanced Encryption Standard

inferredcites →https://doi.org/10.1109/dftvs.2004.1347833openalex-snapshot

An efficient hardware-based fault diagnosis scheme for AES: performances and cost

inferredcites →https://doi.org/10.1109/isvlsi.2004.1339512openalex-snapshot

Minimum area cost for a 30 to 70 Gbits/s AES processor

inferredcites →https://doi.org/10.1109/jssc.2002.808300openalex-snapshot

Design and performance testing of a 2.29-GB/s rijndael processor

inferredcites →https://doi.org/10.1109/massp.1985.1163741openalex-snapshot

VLSI Array processors

inferredcites →https://doi.org/10.1109/tc.2003.1190589openalex-snapshot

A highly regular and scalable aes hardware architecture

inferredcites →https://doi.org/10.1109/tc.2003.1190590openalex-snapshot

Error analysis and detection procedures for a hardware implementation of the advanced encryption standard

inferredcites →https://doi.org/10.1109/test.2003.1271078openalex-snapshot

Parity-based concurrent error detection in symmetric block ciphers

inferredcites →https://doi.org/10.1109/tvlsi.2004.832943openalex-snapshot

High-speed VLSI architectures for the AES algorithm

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/9780470050118.ecse152openalex-snapshot

Algorithm‐Based Fault‐Tolerant Cryptography

inferred← citeshttps://doi.org/10.1007/978-3-540-85053-3_7openalex-snapshot

High-Performance Concurrent Error Detection Scheme for AES Hardware

inferred← citeshttps://doi.org/10.1007/978-3-540-85053-3_8openalex-snapshot

A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis

inferred← citeshttps://doi.org/10.1007/978-3-642-17619-7_3openalex-snapshot

An Algorithm Based Concurrent Error Detection Scheme for AES

inferred← citeshttps://doi.org/10.1007/s10836-009-5108-4openalex-snapshot

Fault Detection Structures of the S-boxes and the Inverse S-boxes for the Advanced Encryption Standard

inferred← citeshttps://doi.org/10.1007/s10836-016-5598-9openalex-snapshot

A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack

inferred← citeshttps://doi.org/10.1109/access.2022.3183764openalex-snapshot

Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher

inferred← citeshttps://doi.org/10.1109/access.2025.3533611openalex-snapshot

Lightweight AES Design for IoT Applications: Optimizations in FPGA and ASIC With DFA Countermeasure Strategies

inferred← citeshttps://doi.org/10.1109/aspdac.2016.7428087openalex-snapshot

Assessing CPA resistance of AES with different fault tolerance mechanisms

inferred← citeshttps://doi.org/10.1109/ccece.2006.277491openalex-snapshot

Parity Prediction of S-Box for AES

inferred← citeshttps://doi.org/10.1109/cit.2010.121openalex-snapshot

Concurrent Error Detection for Multiplicative Inversion of Advanced Encryption Standard

inferred← citeshttps://doi.org/10.1109/ddecs.2009.5012143openalex-snapshot

Round-level concurrent error detection applied to Advanced Encryption Standard

inferred← citeshttps://doi.org/10.1109/dft.2006.50openalex-snapshot

Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard

inferred← citeshttps://doi.org/10.1109/dft.2007.41openalex-snapshot

Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections

inferred← citeshttps://doi.org/10.1109/fdtc.2007.1openalex-snapshot

Workshop on Fault Diagnosis and Tolerance in Cryptography-Title

inferred← citeshttps://doi.org/10.1109/fdtc.2007.2openalex-snapshot

A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard

inferred← citeshttps://doi.org/10.1109/fdtc.2007.8openalex-snapshot

A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection

inferred← citeshttps://doi.org/10.1109/hst.2010.5513109openalex-snapshot

SLICED: Slide-based concurrent error detection technique for symmetric block ciphers

inferred← citeshttps://doi.org/10.1109/idt.2007.4437419openalex-snapshot

Multi-cycle Fault Injections in Error Detecting Implementations of the Advanced Encryption Standard

inferred← citeshttps://doi.org/10.1109/iscas.2008.4541400openalex-snapshot

A fault-tolerant, DFA-resistant AES core

inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180451openalex-snapshot

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers

inferred← citeshttps://doi.org/10.1109/isvlsi.2018.00031openalex-snapshot

A Short Survey at the Intersection of Reliability and Security in Processor Architecture Designs

inferred← citeshttps://doi.org/10.1109/reconfig.2014.7032555openalex-snapshot

Side-channel power analysis of different protection schemes against fault attacks on AES

inferred← citeshttps://doi.org/10.1109/saci.2009.5136262openalex-snapshot

Built-in self test applicability for the non-linear operations of Advanced Encryption Standard

inferred← citeshttps://doi.org/10.1109/tc.2007.1015openalex-snapshot

An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers

inferred← citeshttps://doi.org/10.1109/tc.2008.149openalex-snapshot

Double-Data-Rate Computation as a Countermeasure against Fault Analysis

inferred← citeshttps://doi.org/10.1109/tc.2010.33openalex-snapshot

Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard

inferred← citeshttps://doi.org/10.1109/tc.2011.85openalex-snapshot

A Low-Power High-Performance Concurrent Fault Detection Approach for the Composite Field S-Box and Inverse S-Box

inferred← citeshttps://doi.org/10.1109/tvlsi.2009.2031651openalex-snapshot

A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields

inferred← citeshttps://doi.org/10.1142/s0218126616501139openalex-snapshot

A Fault Tolerant Parallelism Approach for Implementing High-Throughput Pipelined Advanced Encryption Standard

inferred← citeshttps://doi.org/10.1145/1150343.1150393openalex-snapshot

A cryptography core tolerant to DFA fault attacks

inferred← citeshttps://doi.org/10.1145/3194554.3194649openalex-snapshot

Hardening AES Hardware Implementations Against Fault and Error Inject Attacks

inferred← citeshttps://doi.org/10.1587/transfun.e94.a.1971openalex-snapshot

High-Performance Architecture for Concurrent Error Detection for AES Processors

inferred← citeshttps://doi.org/10.21275/art20164149openalex-snapshot

A Survey on Advanced Encryption Standard

inferred← citeshttps://doi.org/10.29292/jics.v2i1.231openalex-snapshot

A Cryptography Core Tolerant to DFA Fault Attacks

inferred← citeshttps://doi.org/10.3390/app12052443openalex-snapshot

Hardware Countermeasures Benchmarking against Fault Attacks

inferred← citeshttps://doi.org/10.3390/s24051598openalex-snapshot

Protecting FPGA-Based Cryptohardware Implementations from Fault Attacks Using ADCs

inferred← citeshttps://doi.org/10.5281/zenodo.1062545openalex-snapshot

Introducing A Platform For Encryption Algorithms

inferred← citeshttps://doi.org/10.6633/ijns.201307.15(4).08openalex-snapshot

A Hybrid Fault Tolerant Approach for AES

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