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Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard

https://doi.org/10.1109/dft.2006.50

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/1-4020-8147-2_12openalex-snapshot

Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard

inferredcites →https://doi.org/10.1007/3-540-45682-1_15openalex-snapshot

A Compact Rijndael Hardware Architecture with S-Box Optimization

inferredcites →https://doi.org/10.1007/s001450010016openalex-snapshot

On the Importance of Eliminating Errors in Cryptographic Computations

inferredcites →https://doi.org/10.1080/0161-110291890876openalex-snapshot

THE ADVANCED ENCRYPTION STANDARD

inferredcites →https://doi.org/10.1109/ccece.2006.277491openalex-snapshot

Parity Prediction of S-Box for AES

inferredcites →https://doi.org/10.1109/dftvs.2001.966796openalex-snapshot

Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture

inferredcites →https://doi.org/10.1109/dftvs.2004.1347833openalex-snapshot

An efficient hardware-based fault diagnosis scheme for AES: performances and cost

inferredcites →https://doi.org/10.1109/dftvs.2005.41openalex-snapshot

Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard

inferredcites →https://doi.org/10.1109/tc.2003.1190590openalex-snapshot

Error analysis and detection procedures for a hardware implementation of the advanced encryption standard

inferredcites →https://doi.org/10.1109/tc.2006.147openalex-snapshot

Fault Detection Architectures for Field Multiplication Using Polynomial Bases

inferredcites →https://doi.org/10.1109/tc.2006.49openalex-snapshot

Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors

inferredcites →https://doi.org/10.1109/tc.2006.90openalex-snapshot

Simple error detection methods for hardware implementation of Advanced Encryption Standard

inferredcites →https://doi.org/10.1109/test.2004.1387397openalex-snapshot

Low cost concurrent error detection for the advanced encryption standard

inferredcites →https://doi.org/10.1109/tvlsi.2004.832943openalex-snapshot

High-speed VLSI architectures for the AES algorithm

inferredcites →https://doi.org/10.1201/9781003337768openalex-snapshot

Cryptography and Network Security

inferredcites →https://doi.org/10.21236/ada434781openalex-snapshot

A Very Compact Rijndael S-box

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Algorithm‐Based Fault‐Tolerant Cryptography

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Error‐correcting cryptographic S‐boxes with multiple error detection and correction

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Fault Attacks on AES and Their Countermeasures

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High-Performance Concurrent Error Detection Scheme for AES Hardware

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A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis

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Security in sequence: NIST-adherent design of a hybrid random number generator with SRAM-based PUF

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Fault Detection Structures of the S-boxes and the Inverse S-boxes for the Advanced Encryption Standard

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A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

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A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack

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Fault-tolerant and error-correcting 4-bit S-boxes for cryptography applications with multiple errors detection

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