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Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.mejo.2005.03.006openalex-snapshot
Timing analysis of network on chip architectures for MP-SoC platforms
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/92.645071openalex-snapshot
Low-power encodings for global communication in CMOS VLSI
inferredcites →https://doi.org/10.1109/dac.2003.1219038openalex-snapshot
System-on-chip beyond the nanometer wall
inferredcites →https://doi.org/10.1109/dac.2003.1219148openalex-snapshot
A survey of techniques for energy efficient on-chip communication
inferredcites →https://doi.org/10.1109/date.2004.1268897openalex-snapshot
Why transition coding for power minimization of on-chip buses does not work
inferredcites →https://doi.org/10.1109/hpca.2003.1183527openalex-snapshot
Dynamic voltage scaling with links for power optimization of interconnection networks
inferredcites →https://doi.org/10.1109/iccd.2004.1347970openalex-snapshot
Design-space exploration of power-aware on/off interconnection networks
inferredcites →https://doi.org/10.1109/icvd.2005.65openalex-snapshot
Coding for reliable on-chip buses: fundamental limits and practical codes
inferredcites →https://doi.org/10.1109/tc.2005.134openalex-snapshot
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
inferredcites →https://doi.org/10.1109/tvlsi.2002.1043337openalex-snapshot
A bus energy model for deep submicron technology
inferredcites →https://doi.org/10.1109/tvlsi.2005.848816openalex-snapshot
Coding for system-on-chip networks: a unified framework
inferredcites →https://doi.org/10.1145/775832.775943openalex-snapshot
System-on-chip beyond the nanometer wall
inferredcites →https://doi.org/10.1145/775832.776059openalex-snapshot
A survey of techniques for energy efficient on-chip communication
inferredcites →https://doi.org/10.5555/968878.969000openalex-snapshot
Why transition coding for power minimization of on-chip buses does not work
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/spe.2796openalex-snapshot
An energy efficient and low overhead fault mitigation technique for internet of thing edge devices reliable on‐chip communication
inferred← citeshttps://doi.org/10.1007/978-981-15-8391-9_21openalex-snapshot
Transition Based Odd/Full Invert Coding Scheme for Crosstalk Avoidance and Low Power Consumption in NoC Links
inferred← citeshttps://doi.org/10.1007/978-981-99-0055-8_18openalex-snapshot
Coupling Transition Reduction on On-Chip Buses Using Adaptive Bus Encoding (ABE)
inferred← citeshttps://doi.org/10.1007/s10836-007-5035-1openalex-snapshot
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding
inferred← citeshttps://doi.org/10.1007/s12530-025-09780-zopenalex-snapshot
ALPS: adaptive low power encoding scheme for networks on chip
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2012.09.013openalex-snapshot
Learning-based adaptation to applications and environments in a reconfigurable network-on-chip for reducing crosstalk and dynamic power consumption
inferred← citeshttps://doi.org/10.1016/j.jpdc.2014.01.002openalex-snapshot
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
inferred← citeshttps://doi.org/10.1016/j.microrel.2021.114296openalex-snapshot
Crosstalk aware transient error correction coding technique for NoC links
inferred← citeshttps://doi.org/10.1049/iet-cdt:20070084openalex-snapshot
Computer-aided crosstalk minimisation design for system-on-chip
inferred← citeshttps://doi.org/10.1049/pbcs030e_ch11openalex-snapshot
3D NoC: a promising alternative for tomorrow's nanosystem design
inferred← citeshttps://doi.org/10.1109/cisp.2009.5301470openalex-snapshot
An Encoding Drive Approach to Reduce Signal Jitter of Interconnection Lines between NoC Routers
inferred← citeshttps://doi.org/10.1109/dft.2006.22openalex-snapshot
Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding
inferred← citeshttps://doi.org/10.1109/dsd.2009.207openalex-snapshot
Low Power Encoding in NoCs Based on Coupling Transition Avoidance
inferred← citeshttps://doi.org/10.1109/icccas.2007.4348257openalex-snapshot
Crosstalk Minimization Method for System-on-Chip
inferred← citeshttps://doi.org/10.1109/icices.2014.7034069openalex-snapshot
Reducing energy consumption using data encoding techniques in network on chip
inferred← citeshttps://doi.org/10.1109/iscas.2018.8351501openalex-snapshot
Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip
inferred← citeshttps://doi.org/10.1109/scopes.2016.7955729openalex-snapshot
Vlsi design of low power data encoding techniques for network-on-chip
inferred← citeshttps://doi.org/10.1109/tetc.2017.2787549openalex-snapshot
Joint Crosstalk Aware Burst Error Fault Tolerance Mechanism for Reliable on-Chip Communication
inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2251020openalex-snapshot
Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip
inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2278334openalex-snapshot
Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip
inferred← citeshttps://doi.org/10.1201/9781315216072openalex-snapshot
Network-on-Chip: The Next Generation of System-on-Chip Integration
inferred← citeshttps://doi.org/10.1201/9781315216072-7openalex-snapshot
Signal Integrity and Reliability of Network-on-Chip
inferred← citeshttps://doi.org/10.1201/b17748-8openalex-snapshot
Signal Integrity and Reliability of Network-on-Chip
inferred← citeshttps://doi.org/10.2991/icmemtc-16.2016.315openalex-snapshot
Research on Fault-Tolerant Routing Mechanism of NoC
inferred← citeshttps://doi.org/10.5772/intechopen.83561openalex-snapshot
Combined Crosstalk Avoidance Code with Error Control Code for Detection and Correction of Random and Burst Errors
inferred← citeshttps://doi.org/10.9756/bijrce.10444openalex-snapshot
Simulation Results for a Crosstalk Avoidance and Low Power Coding Scheme for System on Chips
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