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Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/047120644xopenalex-snapshot
Self‐Similar Network Traffic and Performance Evaluation
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A Theorem on the Distribution of Weights in a Systematic Code†
inferredcites →https://doi.org/10.1016/j.mejo.2005.03.006openalex-snapshot
Timing analysis of network on chip architectures for MP-SoC platforms
inferredcites →https://doi.org/10.1109/16.992868openalex-snapshot
Technology and reliability constrained future copper interconnects. II. Performance implications
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/92.645071openalex-snapshot
Low-power encodings for global communication in CMOS VLSI
inferredcites →https://doi.org/10.1109/dac.2003.1219038openalex-snapshot
System-on-chip beyond the nanometer wall
inferredcites →https://doi.org/10.1109/date.2004.1268897openalex-snapshot
Why transition coding for power minimization of on-chip buses does not work
inferredcites →https://doi.org/10.1109/dsd.2006.49openalex-snapshot
Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm
inferredcites →https://doi.org/10.1109/hpca.2003.1183527openalex-snapshot
Dynamic voltage scaling with links for power optimization of interconnection networks
inferredcites →https://doi.org/10.1109/iccd.2004.1347970openalex-snapshot
Design-space exploration of power-aware on/off interconnection networks
inferredcites →https://doi.org/10.1109/icvd.2005.65openalex-snapshot
Coding for reliable on-chip buses: fundamental limits and practical codes
inferredcites →https://doi.org/10.1109/ipps.1999.760449openalex-snapshot
Performance evaluation of the ServerNet(R) SAN under self-similar traffic
inferredcites →https://doi.org/10.1109/isqed.2004.1283698openalex-snapshot
A scalable communication-centric SoC interconnect architecture
inferredcites →https://doi.org/10.1109/mc.2005.70openalex-snapshot
Robust system design with built-in soft-error resilience
inferredcites →https://doi.org/10.1109/mcas.2004.1330747openalex-snapshot
Feature - Xpipes : a network-on-chip architecture for gigascale systems-on-chip
inferredcites →https://doi.org/10.1109/mdt.2002.1003798openalex-snapshot
Embedded robustness IPs for transient-error-free ICs
inferredcites →https://doi.org/10.1109/mdt.2005.10openalex-snapshot
Exploiting ECC redundancy to minimize crosstalk impact
inferredcites →https://doi.org/10.1109/mdt.2005.104openalex-snapshot
Analysis of error recovery schemes for networks on chips
inferredcites →https://doi.org/10.1109/mdt.2005.91openalex-snapshot
New ECC for crosstalk impact minimization
inferredcites →https://doi.org/10.1109/olt.2002.1030176openalex-snapshot
Coding scheme for low energy consumption fault-tolerant bus
inferredcites →https://doi.org/10.1109/olt.2003.1214368openalex-snapshot
Power consumption of fault tolerant codes: the active elements
inferredcites →https://doi.org/10.1109/socc.2006.283886openalex-snapshot
Crosstalk-aware Energy Reduction in NoC Communication Fabrics
inferredcites →https://doi.org/10.1109/tc.2005.134openalex-snapshot
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
inferredcites →https://doi.org/10.1109/tcad.2005.847907openalex-snapshot
Error control schemes for on-chip communication links: the energy-reliability tradeoff
inferredcites →https://doi.org/10.1109/tvlsi.2002.1043337openalex-snapshot
A bus energy model for deep submicron technology
inferredcites →https://doi.org/10.1109/tvlsi.2004.827565openalex-snapshot
Error-correction and crosstalk avoidance in DSM busses
inferredcites →https://doi.org/10.1109/tvlsi.2005.848816openalex-snapshot
Coding for system-on-chip networks: a unified framework
inferredcites →https://doi.org/10.1145/639929.639933openalex-snapshot
Error-correction and crosstalk avoidance in DSM busses
inferredcites →https://doi.org/10.1145/775832.775943openalex-snapshot
System-on-chip beyond the nanometer wall
inferredcites →https://doi.org/10.5555/603095.603107openalex-snapshot
Bus encoding to prevent crosstalk delay
inferredcites →https://doi.org/10.5555/968878.969000openalex-snapshot
Why transition coding for power minimization of on-chip buses does not work
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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An energy efficient and low overhead fault mitigation technique for internet of thing edge devices reliable on‐chip communication
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Solutions to Improve the Reliability of On-Chip Interconnects
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Existing Transient and Permanent Error Management in NoCs
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Adaptive Error Control Coding at Datalink Layer
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Addressing NoC Reliability Through an Efficient Fibonacci-Based Crosstalk Avoidance Codec Design
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Design and Testing of Low Power Reliable NoCs for Wireless Applications
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Built-in Self Test Power and Test Time Analysis in On-chip Networks
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Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding
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Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link
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A New Approach to Model the Effect of Topology on Testing Using Boundary Scan
inferred← citeshttps://doi.org/10.1016/b978-012373973-5.50009-7openalex-snapshot
System/Network-On-Chip Test Architectures
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A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips
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Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.12.008openalex-snapshot
Reliable low power NoC interconnect
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OP-Fibo: An efficient Forbidden Pattern Free CAC design
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Adaptive error control for nanometer scale network-on-chip links
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Design and evaluation of a high throughput robust router for network-on-chip
inferred← citeshttps://doi.org/10.1049/iet-cdt.2015.0131openalex-snapshot
Performance/energy aware task migration algorithm for many‐core chips
inferred← citeshttps://doi.org/10.1049/iet-cdt.2019.0082openalex-snapshot
Power efficient error correction coding for on‐chip interconnection links
inferred← citeshttps://doi.org/10.1109/ahs.2017.8046371openalex-snapshot
Design of reconfigurable and reliable application specific network on chip for R3TOS
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A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip
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An Efficient Method to Reliable Data Transmission in Network-on-Chips
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Design of R3TOS based reliable low power network on chip
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Random and Triple burst error correction code with low redundancy for Network-on-Chip link
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Crosstalk mitigation of network on chip: An analytical review
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Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics
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Configurable Error Control Scheme for NoC Signal Integrity
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Essential Fault-Tolerance Metrics for NoC Infrastructures
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Bounds on asymptotic rate of capacitive crosstalk avoidance codes for on-chip buses
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Crosstalk avoidance coding for reliable data transmission of network on chips
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Addressing Signal Integrity in Networks on Chip Interconnects through Crosstalk-Aware Double Error Correction Coding
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NoC interconnection functional testing: Using boundary-scan to reduce the overall testing time
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Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip
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FiRot: An Efficient Crosstalk Mitigation Method for Network-on-Chips
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S2AP: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NoCs
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A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip
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At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs
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Redefining and testing interconnect faults in Mesh NoCs
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Joint Crosstalk Aware Burst Error Fault Tolerance Mechanism for Reliable on-Chip Communication
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HREN: A Hybrid Reliable and Energy-Efficient Network-on-Chip Architecture
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Joint Crosstalk-Avoidance and Error-Correction Coding for Parallel Data Buses
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An Energy‐Efficient Multiwire Error Control Scheme for Reliable On‐Chip Interconnects Using Hamming Product Codes
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Self‐Calibrated Energy‐Efficient and Reliable Channels for On‐Chip Interconnection Networks
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Signal Integrity and Reliability of Network-on-Chip
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Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link
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Bounds on the Asymptotic Rate for Capacitive Crosstalk Avoidance Codes for On-Chip Buses
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System-Level Design of NoC-Based Dependable Embedded Systems
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System-Level Design of NoC-Based Dependable Embedded Systems
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Self-Repair Technology for Global Interconnects on SoCs
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Bounds on Asymptotic Rate of Capacitive Crosstalk Avoidance Codes for On-chip Buses
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Combined Crosstalk Avoidance Code with Error Control Code for Detection and Correction of Random and Burst Errors
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Stratégie de fiabilisation au niveau système des architectures MPSoC
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